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[From Analog Devices Data Converter Handbook]

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I understand why they chose to place the first transition at the 1/2 LSB point but does that not cause non-linearity?, since you basically have reduced the probability that a 000 code could occur?

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    \$\begingroup\$ Think back to junior high geometry, y=mx+b. What you are describing, if you want to argue it is even a flaw at all (which is dubious) is at most change in b, or the offset. Still linear. Non-linearity would only occur if the spacing between the transitions points were unequal. \$\endgroup\$ Oct 11 '19 at 23:38
  • \$\begingroup\$ Okay, maybe that was a bad explanation. It is linear but is it not at a flaw? For an analog input range of 0 to 1/2LSB, the ADC produces 000. But from 1/2 LSB to 3/2 LSB, the ADC produces 001? \$\endgroup\$ Oct 11 '19 at 23:40
  • \$\begingroup\$ @ChrisStratton Is that not the case though? The first transition region occurs at 1/2LSB and the second transition region occurs at 3/2LSB. Third transition region occurs at 2.5 LSB. Actually that is a 1 LSB difference each time. I just can't understand by looking at the graph how that's okay. The 000 digital code has a smaller analog input than the other codes. Doesn't sit well within my head. \$\endgroup\$ Oct 11 '19 at 23:44
  • \$\begingroup\$ This ADC sample is single ended, if you extend the graph to negative you will see that each value is valid/represented with exactly 1lsb wide equivalent analog range (-0.5 to 0.5 lsb in this case) . This graph is cut at v>0 \$\endgroup\$
    – crasic
    Oct 12 '19 at 1:51
  • \$\begingroup\$ Additionally, even in single ended regime. Your application should not be really care to resolve such difference between 0/1lsb. The effective noise free bits are always less than the total number of bits, and are not related to linearity spec at all. Code words with difference of 1 lsb are redundant in a complicated manner due to noise anyway and this minor aberation should do nothing. Note that for an 8bit ADC 1 lsb is 0.25% for a 24 bit ADC it is approx 30 part per billion, equivalent to -150db. Oh boy \$\endgroup\$
    – crasic
    Oct 12 '19 at 1:58
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Unlike the LSB code, which can only have certain discrete values, the analog input is a real, physical, continuous voltage input, which can go above full scale and below zero (even if that violates existing table or abs max rating). What’s misleading is that the graph makes it look like the analog input range for code 0 is smaller than the others, when in fact it is the same size. It’s just that the left half of the code 0 input voltage range is below zero volts, so it is not show on this graph. If they extended the horizontal axis to include negative input voltage, it would be a straight line extending through the “missing” half of the nominal code 0 range, and continuing at 0 as the lower saturation limit, just like the full scale limit does. When you look at a bipolar ADC transfer function, it’s more obvious because the 0 voltage 0 LSB code point is in the center, with positive and negative full scale staircases in opposite directions. This unipolar ADC transfer function graph just looks weird because of where they stopped the horizontal axis.

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  • \$\begingroup\$ That make so much sense!!!! Thank you so much. \$\endgroup\$ Oct 12 '19 at 13:02
  • \$\begingroup\$ So is it possible to take the straight line at the transition points, rather than the code center? Then you would get a full LSB for the code 0 and last code while still being unipolar? \$\endgroup\$ Oct 12 '19 at 13:06
  • \$\begingroup\$ Also - I'm assuming nobody uses that plot when calculating DNL right? Because in that case, the first and last code would always give a -0.5LSB error to the DNL? Or do they compare the first and the last code to 0.5LSB rather than the ideal 1? \$\endgroup\$ Oct 12 '19 at 13:38
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A typical ADC gets very, very nonlinear as you hit the saturation. The 1/2 LSB is just the tip of it, since it reads 0 for any voltage below 0. It’s all kind of theoretical anyway since most ADCs have more than 1/2 LSB of offset voltage.

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I disagree with that article.

First, note that not only is the LH (000) interval only 0.5 LSB wide, but also the RH (111) interval is 1.5 LSBs wide.

So, making the bit transition happen on the LSB interval instead of half an LSB below it makes for a symmetrical plot with all intervals the same size. Note that this is exactly equivalent to truncating the analog input voltage, instead of rounding it (up or down) to the nearest bit code.

And in fact that's what happens in an ideal model of an ADC : the reference voltage is divided in a resistive ladder into a series of steps, and the input voltage is compared with one of those steps. If it is equal or above, that bit is '1', otherwise '0'. There is not normally means of adding 0.5 LSB to one side of the comparison or subtracting it from the other.

(This glosses over details of successive approximation, and imperfect circuitry with DC offsets and resistor inaccuracies muddies the picture in practice)

You can achieve the situation described in the article, however, and it doesn't involve any non-linearity. It just requires a DC offset of +0.5 LSB added to the analog input. So there is little difference in practice, especially when the value of 1 LSB is comparable to (or smaller than) DC offsets encountered in the analog input stages.

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The benefit of this transfer function is that it reduces the maximum quantization error to \$\pm\$1/2 LSB and yields an average quantization error of zero.

If the width of the first step was as wide as the LSB voltage, then the maximum quantization error would be 1 LSB and the average quantization error would be 1/2 LSB.

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