Generally Flip-Flops are used, but Latches are also usefull in some situations.
Flip-Flops are easiest to use with state machines. Flip-Flops only change on the rising (or falling) edge of the clock. Their data input should not change during a timeframe near that clock edge - this timeframe is defined by the 'setup time' and the 'hold time'.
Latches are not triggered by the clock edge, but they are "open" or "closed" depending on the gate (or enable) signal. While they are open the standard output (generally Q) will follow the data input. To have a deterministic behavior, they also require that the data input is stable during a given time frame near the "falling edge" of the enable signal (if the latch is open when the enable signal is high).
The Flip-Flop and Latch outputs define states of the state machine.
In case of Flip-Flops, the new states are stable until the next clock edge. When the Flip-Flop output changes, this new output is presented to the "next" Flip-Flop (after passing through combinational logic if any). This "next" Flip-Flop will ignore the change because the clock edge happened before the data input change. Therefore, the system is stable just after the clock edge.
With Latches, when the gates are opened, the output also changes (the same as with Flip-Flops), but the next latch (using the same enable signal) will propagate the data input change immediately (because the next latch is still open). This output change may have an impact on the output of the first Latch, which changes its output again, in which case the second Latch also changes its output. This can result in an unstable system.
But Latches also have advantages over Flip-Flops:
- They are smaller;
- They do not require steep clock edges (resulting in lower EMC emissions).
And there are techniques to use them:
- Use the Latches in a Master-Slave Flip-Flop
- Design the state-machine so that there is only one bit change at a time.
1. Master-Slave Flip Flop
In a Master-Slave Flip Flop, two latches are connected in series and only one latch is open at a time. This solves the issue of data propagation.
2. State-Machine with one bit change at a time.
Most state machines that we know will have multiple bits of its state that change following a clock change.
But if you ensure that only one bit can change at a time in the state machine in one clock cycle, you can build a state machine using latches. There is a methodology to do so.
3. Phased clocks
It is also possible to make sure that latches that are interconnected with combinational logic use different clocks that are not active at the same time. The principle is more or less the same as with master-slave flip-flops, but it is possible to have only one latch for a state (with Master Slave Flip Flops, there are always two latches for a state).
I have used Master-Slave Flip-Flops (MSFF) in a project where it was important to keep EMC emissions low. It used MSFF with slow slopes and phased clock signals with slow slopes.