I was reading about flip flops where author is convincing that it's better to use flip flop than latches. He gave following reason for it.

As seen from the block diagram of Fig. 5.2. a sequential circuit has a feedback path from the output of the flip-flop to the input of the combinational circuit.Consequently, the inputs of the flip-flops are derived in part from the output of the same and other flip-flops.When latches are used for the storage elements, a serious difficulty arise. The state transition of the latches start as soon as the clock pulse changes to the logic-I level.The new state of a latch appears at the output while the pulse is still active.This output is connected to the inputs of the latches through the combinational circuit. If the inputs applied to the latches change while the clock pulse is still at the logic-I level. the latches will respond to new values and a new output state may occur. The result is an unpredictable situation.since the state of the latches may keep changing for as long as the clock pulses stays at the active level. Because of this unreliable operation. The output of a latches cannot be applied directly or through combinational logic to the input of the same or an- other latch when all the latches are triggered by a common clock signal'.

Can anyone explain me in simpler language what author actually want to convey to the reader. Or can explain in his own words for better understanding. Thanks in advance.

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    \$\begingroup\$ Well that depends. Do you want your memory to latch with time sensitivity or do you want to control when your memory changes? Typically you want your memory to be time sensitive because you don't want your memory to be in some funky state. \$\endgroup\$ – user103380 Oct 12 '19 at 23:14
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    \$\begingroup\$ read the datasheets on the 7475 latch or the 7474 D FF \$\endgroup\$ – analogsystemsrf Oct 13 '19 at 4:05

Generally Flip-Flops are used, but Latches are also usefull in some situations.

Flip-Flops are easiest to use with state machines. Flip-Flops only change on the rising (or falling) edge of the clock. Their data input should not change during a timeframe near that clock edge - this timeframe is defined by the 'setup time' and the 'hold time'.

Latches are not triggered by the clock edge, but they are "open" or "closed" depending on the gate (or enable) signal. While they are open the standard output (generally Q) will follow the data input. To have a deterministic behavior, they also require that the data input is stable during a given time frame near the "falling edge" of the enable signal (if the latch is open when the enable signal is high).

The Flip-Flop and Latch outputs define states of the state machine.

In case of Flip-Flops, the new states are stable until the next clock edge. When the Flip-Flop output changes, this new output is presented to the "next" Flip-Flop (after passing through combinational logic if any). This "next" Flip-Flop will ignore the change because the clock edge happened before the data input change. Therefore, the system is stable just after the clock edge.

With Latches, when the gates are opened, the output also changes (the same as with Flip-Flops), but the next latch (using the same enable signal) will propagate the data input change immediately (because the next latch is still open). This output change may have an impact on the output of the first Latch, which changes its output again, in which case the second Latch also changes its output. This can result in an unstable system.

But Latches also have advantages over Flip-Flops:

  • They are smaller;
  • They do not require steep clock edges (resulting in lower EMC emissions).

And there are techniques to use them:

  1. Use the Latches in a Master-Slave Flip-Flop
  2. Design the state-machine so that there is only one bit change at a time.

1. Master-Slave Flip Flop

In a Master-Slave Flip Flop, two latches are connected in series and only one latch is open at a time. This solves the issue of data propagation.

2. State-Machine with one bit change at a time.

Most state machines that we know will have multiple bits of its state that change following a clock change. But if you ensure that only one bit can change at a time in the state machine in one clock cycle, you can build a state machine using latches. There is a methodology to do so.

3. Phased clocks

It is also possible to make sure that latches that are interconnected with combinational logic use different clocks that are not active at the same time. The principle is more or less the same as with master-slave flip-flops, but it is possible to have only one latch for a state (with Master Slave Flip Flops, there are always two latches for a state).

Final word

I have used Master-Slave Flip-Flops (MSFF) in a project where it was important to keep EMC emissions low. It used MSFF with slow slopes and phased clock signals with slow slopes.


Sequential circuit is basically composed of combinational circuit which takes output from the storage element like flip-flop or latch and stores its output to another storage element.

Flip-flop(s) avoid any change for the input(s) of the combinational circuits during a whole clock period. And therefore, combinational circuit can compute its output(s) in this period as its input(s) are not changed for surely during this period.

However, if latch is used, latches differently than flip flops allow any change (high to low or low to high) for the high clock duration. This means that the input(s) of the combinational circuit can change while the combinational circuit is trying to compute the output(s). This change propagates through the combinational circuit and may change some of the output(s) while some others may not be changed due to high path delays. This results in wrong output(s). Output(s) become non-deterministic depending on the time of input change and the path delay of each output.


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