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I am simulating a current step in a buck converter with a resistive load that I designed. I am measuring the response while stepping the current up from 5A to 10A and stepping the current down from 10A to 5A.

It appears that the settling time is around double in the current step down scenario (~6ms) in comparison to the step up scenario (~3ms). Intuitively, I would've expected the settling time to be the same in both scenarios. Does anybody know why is this happening? Thanks.

The circuit:

enter image description here

Inductor current and output voltage in a step up from 5A to 10A:

enter image description here

Inductor current and output voltage in a step down from 10A to 5A:

enter image description here

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The characteristics of a passive network like this are very much dependent on the load impedance it sees. Obviously, the step-up scenario has half the load impedance of the step-down scenario, and this provides greater damping (lower "Q").

If your converter had feedback and dynamic control of the switching duty cycle, you could pretty much eliminate these effects.

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  • \$\begingroup\$ Thank you for the info! I'm trying to intuitively understand the proportional relationship between Q and R in this circuit. As this is an series L/parallel C/parallel R circuit and not a simple series/parallel RLC circuit, you could derive the Q factor of the circuit manually by deriving the resonant frequency and bandwidth. How do you intuitively know that Q is proportional to R without deriving the equation manually? \$\endgroup\$
    – w00t
    Commented Oct 13, 2019 at 7:21
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    \$\begingroup\$ But it IS a parallel LCR circuit -- regardless of whether the switch is open or closed, for the purposes of AC analysis, the left end of the coil is effectively shorted to ground, either through the voltage source, or through the diode. \$\endgroup\$
    – Dave Tweed
    Commented Oct 13, 2019 at 11:15
  • \$\begingroup\$ Understood, thank you! \$\endgroup\$
    – w00t
    Commented Oct 13, 2019 at 18:17

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