# 4 Channel NOT and AND Gate Symbols

I am designing an ALU for my computer architecture class. The rubric states that we need to simplify each logical part to make it as clear as possible. My group condensed the 4 NOT gates and 4 AND gates into their own components which are still represented using the NOT and AND gate symbols.

Question: Using the AND and NOT gate symbols, is it correct that they have multiple outputs? Or should their symbols now be rectangles with a title because they are a 'non standard' component?

Before

After

EDIT: I had to remove the entire schematic images because this assignment isn't due yet and other teams could potentially cheat. I hope this is still helpful!

• IMHO (as a student doing both analog and digital undergrad EE) the second image is far more confusing, especially with regard to the AND and the mux. The first seems to pretty adequately convey the logical design of your schematic with relatively neat uses of rows/columns, while the second represents the physical construction (i.e. gates mapped to chips) while sacrificing one's ability to understand its logic. The second also uses non-standard symbols, which are likely to be confusing or counterintuitive. Oct 13, 2019 at 22:36
• @ζ-- Thanks for the help! I agree it is less confusing... Oct 13, 2019 at 22:47

You shouldn't do that.

An AND gate with 4 inputs is a standard symbol. But it only has one output, which is high only if all 4 inputs are high. If you draw a 4-input AND gate and intend it have some other function, you're just going to confuse people.

With your AND gate with 4 outputs, how am I to know which inputs must be high for each output to be high?

And if you want to unclutter a drawing by removing NOT gates, you can do it by using bubble notations on the inputs of whatever those NOT gates drive, not by inventing a new 4-channel NOT-gate symbol.

There are some circumstances in which what you're doing might make sense. But give your symbols buses for the inputs and outputs, rather than individual pins. Then it becomes a bit more clear that the output is a bit-for-bit AND of the two inputs.

It would be the diagrammatic equivalent of writing the following in, say, Verilog:

wire [3:0] a;
wire [3:0] b;
wire [3:0] c;
wire [3:0] d;

assign c = a & b;
assign d = ~a;


If done this way, I think most people would get what you intended.