I have a discrete video controller which reads a image from SRAM. The image should be written by a CPU. So I designed this circuit.

enter image description here

I use two display RAM because I want to use double buffering. So the CPU should only write to the inactive memory.

Is there any option to simplify this circuit, because I think this solution is very complex (especially when I design the PCB).

  • \$\begingroup\$ Why are the address lines of those two memories shared? That doesn't make much sense for double-buffering. \$\endgroup\$ Commented Oct 14, 2019 at 14:31
  • \$\begingroup\$ Because I switch the R/W input of the SRAM, so only the inactive memory is writeable and the other is readable. Would it be a better idea to use two address spaces for double buffering? \$\endgroup\$
    – Kampi
    Commented Oct 14, 2019 at 14:35
  • \$\begingroup\$ Certainly, I'd argue that's the whole point of double-buffering. That way you can freely read/write to one buffer with a CPU, while reading from the other for the graphics output, without caring about any timings on the CPU side (perhaps only fire an interrupt during the vertical back porch to tell the CPU it can switch the buffers now if it's done drawing into its one). \$\endgroup\$ Commented Oct 14, 2019 at 14:39
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    \$\begingroup\$ This would make the PCB more complex yet as you'd not only have to switch the data lines, but also the address lines. Regardless, that's how it should be done (imo). One can also quickly start to see why people would prefer doing such things on an FPGA these days. :D \$\endgroup\$ Commented Oct 14, 2019 at 14:42
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    \$\begingroup\$ First realize that nobody puts this kind of thing on a PCB anymore. If you want something simple you would use dual port memory, otherwise you need a bus arbitration scheme. Consider moving the whole project to an FPGA eval board, or wiring in an entire old ISA VGA card. Or better yet skip VGA - use a modern SoC with either a connectorized digital interface like HDMI or a parallel RGB or MIPI LCD interface, or use an MCU and a small SPI or I2C display. \$\endgroup\$ Commented Oct 14, 2019 at 15:15

1 Answer 1


Actually, that's TOO simple. You haven't provided any way for the CPU's address bus to get to the RAM chips for writing data. Each of the RAM chips needs an address multiplexer in addition to the data buffers that you have. The good news is that the same muxes can probably be used to steer the CPU's write enable to the correct chip as well.

There's another problem as well. I can see why you didn't connect the three LSBs of Pixel, assuming you're only using 1 bit per pixel, but you can't do the same thing with Line. You need ALL of the Line addresses, which means that your RAMs need to be 8× the size — 16 address lines instead of 13, giving you 65 kB of storage (up to 512k pixels). Standard VGA requires 480 × 640 = 300k pixels.

  • \$\begingroup\$ Damit. You are right... I miss the address lines for the CPU... . That´s bad...I have to rethink the whole concept. \$\endgroup\$
    – Kampi
    Commented Oct 14, 2019 at 15:33

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