The controlled impedance is a ratio \$Z_o=\sqrt{L/C}\$ .
Edit:Thinner tracks reduce L and but reduces C slightly more to ground so impedance rises slightly reducing rise time increasing crosstalk emissions. This is corrected by using multilayers with much thinner dielectric height.
Larger coplanar gaps raise impedance and reduce crosstalk capacitance per unit length but also reduces rise time slightly so the gap space/gnd height, or S/H ratio should be > 1.
length of track X pF/cm = capacitance, C
R driver ( 50 typ for 5V logic) X C = Rise time [ns]
e.g. if T rise time is 3 ns into 20 pF load
- with track at H/W=8 =1.0mm/0.125mm with 0.42pF/cm
If the adjacent track is also 1mm it is ~ 0.4pF/cm
A 12cm track length is then 5 pF so the rise time reduces from 3ns @ 20pF accordingly but added to Cin of gate of say 3.5pF for 74HC'
trk trk-trk
Rise time V Length Space FR4 H Crosstalk
1ns 5V 2cm 1.0mm 1.0mm 2.5V
1ns 5V 2cm 0.5mm 1.0mm 4.0V
1ns 5V 2cm 1.0mm 0.5mm 1.0V
1ns 5V 2cm 0.5mm 0.5mm 2.5V
5ns 5V 2cm 1.0mm 1.0mm 1.35V
5ns 5V 2cm 0.5mm 1.0mm 2.16V
5ns 5V 2cm 1.0mm 0.5mm 1.0V
5ns 5V 2cm 0.5mm 0.5mm 1.35V
Crosstalk must be analyzed when it occurs so see if that matters. If it is edge-triggered, then you can see crosstalk is a big issue. But if it is sampled data, then the timing of crosstalk matters.
Track gaps can be reduced with a thin and track for much better results.