Studying the design of many boards, I noticed that the signal lines go very close to each other.

A small distance between the tracks improves noise immunity or is it a matter of beauty and compactness?

I make a large distance between the tracks (0.7-1 mm). Should I reduce it if the size allows?

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    \$\begingroup\$ Without knowing the circuit that is driving these lines and what the frequencies of the signals are, it is impossible to answer this. When the lines are used at a low frequency and/or driven from a low impedance then the spacing can be small without issues. As frequencies go up and driving impedance increases, more space and/or a grounded trace in between is needed. \$\endgroup\$ – Bimpelrekkie Oct 15 '19 at 8:16

Cross-talk can be a problem when two tracks that carry unrelated signals are too close. However, when two tracks are carrying a differential signal, placing the tracks closer together usually improves immunity from unrelated signals.

Placing differential tracks at the right distance relative to each other (neither too close nor too far) allows the "transmission" to have a "purer" characteristic impedance and thus signal reflection problems are reduced.

So, given what I've said, you have to categorize what the signals are before deciding on how to track them. I notice that in your screenshot of the PCB, one track is called TXD and another is called RXD. This implies to me that it is likely that the signals they carry are electrically unrelated and therefore they should be kept apart. However, if you run a ground track between them, they can be closer (for example).


The controlled impedance is a ratio \$Z_o=\sqrt{L/C}\$ .

Edit:Thinner tracks reduce L and but reduces C slightly more to ground so impedance rises slightly reducing rise time increasing crosstalk emissions. This is corrected by using multilayers with much thinner dielectric height.

Larger coplanar gaps raise impedance and reduce crosstalk capacitance per unit length but also reduces rise time slightly so the gap space/gnd height, or S/H ratio should be > 1.

length of track X pF/cm = capacitance, C
R driver ( 50 typ for 5V logic) X C = Rise time [ns]

e.g. if T rise time is 3 ns into 20 pF load
- with track at H/W=8 =1.0mm/0.125mm with 0.42pF/cm
If the adjacent track is also 1mm it is ~ 0.4pF/cm

A 12cm track length is then 5 pF so the rise time reduces from 3ns @ 20pF accordingly but added to Cin of gate of say 3.5pF for 74HC'

                trk   trk-trk
 Rise time  V  Length Space  FR4 H Crosstalk
 1ns       5V  2cm   1.0mm  1.0mm 2.5V
 1ns       5V  2cm   0.5mm  1.0mm 4.0V
 1ns       5V  2cm   1.0mm  0.5mm 1.0V
 1ns       5V  2cm   0.5mm  0.5mm 2.5V

 5ns       5V  2cm   1.0mm  1.0mm 1.35V
 5ns       5V  2cm   0.5mm  1.0mm 2.16V
 5ns       5V  2cm   1.0mm  0.5mm 1.0V
 5ns       5V  2cm   0.5mm  0.5mm 1.35V

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Crosstalk must be analyzed when it occurs so see if that matters. If it is edge-triggered, then you can see crosstalk is a big issue. But if it is sampled data, then the timing of crosstalk matters.

Track gaps can be reduced with a thin and track for much better results.


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