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(This is not a homework question.)

While reading "Digital Computer Electronics" by Albert P. Malvino, I found this circuit on page 121, figure 8-22(a). It claims to be an example of a discrete TTL tri-state buffer, but I believe it to be wrong.

Best I can tell, the output will always be either high or tristated: it will never be low. I also simulated it online, and the results agreed with this assessment. I googled for published errata, but found none.

Would people say this circuit was in error, or am I missing something crucial?

photograph of textbook

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  • \$\begingroup\$ It won't work for driving TTL. Connect it to a TTL input. It cannot sink the required negative 2mA. It would only work with mos input, and then only if a pulldown resistor was added to Dout. (TTL inputs have no such pulldown resistor!) \$\endgroup\$
    – wbeaty
    Oct 16 '19 at 1:22
  • \$\begingroup\$ It won't work for driving CMOS either. Or anything with any sort of pullup. \$\endgroup\$
    – Finbarr
    Oct 16 '19 at 9:58
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For true TTL tri-state operation the output must be able to pull up and down. The circuit in your book can only pull up, which is not compatible with TTL logic.

Here is a real tri-state TTL (inverting) buffer:-

schematic

simulate this circuit – Schematic created using CircuitLab

When Enable is high Q3 is turned on, which turns off Q5 via D1, and Q4 and Q6 via Q1B. Q6 provides the essential pull down when not tri-stated.

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  • \$\begingroup\$ This is pretty much what I figured. Without a pull-down, there are only two states. It's essentially the opposite of an open-collector gate. So the author is wrong, and the other answerers of this question are wrong. \$\endgroup\$ Oct 16 '19 at 21:10
  • \$\begingroup\$ It doesn’t actually say that it is TTL logic compatible anywhere in the text. \$\endgroup\$
    – metacollin
    Oct 18 '19 at 15:32
  • \$\begingroup\$ @metacollin the OP says that it does. 7400 gates are mentioned in a later paragraph, but the text is cut off in the photo so its relevance can't be verified. That is why I was careful to not state that the textbook was wrong. In any case it's a poor example. Why talk about tri-state TTL right after showing a dodgy circuit that isn't TTL compatible? \$\endgroup\$ Oct 18 '19 at 18:45
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Upon finding the original textbook online and reviewing the wording, my previous answer was incorrect so, I reversed my opinion. Apologies for the Senior's moment.

This is NOT a 3 state switch. The text is incorrect.

There is no active open collector to pull down the bus to 0V < 100 ohms for a logic "0" or even 10k for high Zin.

enter image description here enter image description here

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