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I'm designing a CPU architecture. I've come up with a preliminary design: CPU diagram

I'd like general thoughts on what I can improve in the design and also I have some specific questions:

  • Is it overkill to have every register inputting to the ALU, or is it more sensible to have one input hardwired to, say, A?

  • This design is as you can probably tell influenced by the Z80 (hence the register naming). Is it a good idea to base the CPU design off of such an old CPU or does it not make any difference really?

  • I've not decided whether to have a simple instruction register or whether to implement a pipeline. What kind of performance gains might I be able to achieve in a simple CPU design like this? i.e. is it worth the extra effort of constructing a pipeline?

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    \$\begingroup\$ You're getting way ahead of yourself here. You can't design an implementation until you know what your requirements are. You first have to know what instructions you want this CPU to execute -- the Instruction Set Architecture, or ISA. Only then can you start to think about the hardware resources required for implementation (and performance issues). \$\endgroup\$
    – Dave Tweed
    Commented Oct 15, 2019 at 20:44
  • \$\begingroup\$ "Does it make a difference?" I'd say, of course it does, others might not: that's a purely subjective question. If you want to compare this to modern CPU designs: there's actually a wealth of small RISC-V implementations out there, and some are really well documented. \$\endgroup\$ Commented Oct 15, 2019 at 20:44
  • \$\begingroup\$ "Is it overkill?": How should we tell? For what purpose? What's the problem you're having with this? \$\endgroup\$ Commented Oct 15, 2019 at 20:45
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    \$\begingroup\$ @DaveTweed I have an ISA. Should I have posted it here? It's a little out of date as I've altered the hardware design since then but I could make some changes and repost \$\endgroup\$
    – Jachdich
    Commented Oct 15, 2019 at 20:46
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    \$\begingroup\$ All in all, I congratulate you on starting such a large and educative project! Rest assured that you're not going to build a competitely performant CPU on your first iteration, so maybe don't start with optimizing for performance, but for realizability! \$\endgroup\$ Commented Oct 15, 2019 at 20:46

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Is it overkill to have every register inputting to the ALU, or is it more sensible to have one input hardwired to, say, A?

You will need more 'buffers' and connecting logic to route all the registers to the ALU, so you its a space vs functionality trade off.

This design is as you can probably tell influenced by the Z80 (hence the register naming). Is it a good idea to base the CPU design off of such an old CPU or does it not make any difference really?

Older CPUs are easier to understand because they have reduced instruction sets and smaller data widths, I would prefer to design with an old CPU if I were implementing this myself.

I've not decided whether to have a simple instruction register or whether to implement a pipeline. What kind of performance gains might I be able to achieve in a simple CPU design like this? i.e. is it worth the extra effort of constructing a pipeline?

If you don't want to wait for your ALU to complete instructions, you'll want a pipeline.

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  • \$\begingroup\$ think about VLIW, and dump the optimization onto the Compiler. \$\endgroup\$ Commented Oct 16, 2019 at 4:16
  • \$\begingroup\$ @analogsystemsrf, you recommend the OP writes an optimising compiler as well? \$\endgroup\$
    – TonyM
    Commented Oct 16, 2019 at 5:30
  • \$\begingroup\$ @analogsystemsrf from what I understand, you'd have to be a literal wizard to create a CPU that supports VLIW and probably at least 10 wizards to write a compiler that is fairly performant. Heck, I've never written a C compiler before. \$\endgroup\$
    – Jachdich
    Commented Oct 16, 2019 at 7:52
  • \$\begingroup\$ @Jachdich As far as I understand, a VLIW CPU is simpler because there is no instruction decoder. Writing an ideal optimising compiler may be difficult. Writing a simple compiler that doesn't take advantage of the VLIWness should not be. I don't think it will make the CPU easier to design though - you'll still need to consider what kinds of instructions your compiler will realistically need to generate. \$\endgroup\$ Commented Oct 29, 2019 at 15:15
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    \$\begingroup\$ @user253751 so VLIW is just microcode? In that case, it would be easier to implement in hardware. I'm not 100% sure if it is just microcode but I think theres a chance it's more complex than that. \$\endgroup\$
    – Jachdich
    Commented Oct 29, 2019 at 15:18
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Late to the party.

No it's not crazy. How did the CPU come along?

My own homebrew CPU SPAM-1 has all registers (everything) going via the ALU.

https://hackaday.io/project/166922-spam-1-8-bit-cpu

There's a YouTube vid on my register files design.

Or ... https://www.google.com/search?q=spam1+8bit+cpu

The benefit of all regs going via ALU is that you end up with a much more powerful machine language.

Other cpus like the 6502 end up using tax/txa to perform register transfers to get access to the ALU. But you won't need to waste CPU cycles on that.

Not needing to swap regs means simpler faster code

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  • \$\begingroup\$ This could become an answer, if you explain the decision about connecting all registers to the ALU. \$\endgroup\$
    – Jens
    Commented Aug 14, 2022 at 22:21
  • \$\begingroup\$ Done - thoughts? \$\endgroup\$ Commented Aug 15, 2022 at 23:54
  • \$\begingroup\$ Yes, good point \$\endgroup\$
    – Jens
    Commented Aug 16, 2022 at 2:02

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