I'm trying to create parallel to RS-232 serial converter using standard logic (serial transmitter only, no serial receive functionality). To get the clock signal my idea was to get a 7.3728MHz oscillator and then keep dividing the frequency by 2 until I get the desired frequency. This works to get common baud rates such as 460800Hz, 115200Hz, and 57600Hz.

The issue comes when I try to get lower baud rates, such as the standard 9600Hz, because below 57600Hz the frequencies I get aren't standard baud rates. For example, \$57600\div2 = 28800\$. This is no good.

I also can't find any oscillators or crystals online which oscillate at a multiple of 9600Hz. So, how is this usually achieved?


  • \$\begingroup\$ EDIT: I must've not have looked hard enough... I just found a 38.4KHz crystal, which works. I'm still interested if there is a different standard way to do this however. \$\endgroup\$ Commented Oct 16, 2019 at 21:10
  • \$\begingroup\$ en.wikipedia.org/wiki/Crystal_oscillator_frequencies \$\endgroup\$ Commented Oct 16, 2019 at 21:24
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    \$\begingroup\$ Why are you stuck on only dividing by 2? 7.3728MHz / 768 == 9600Hz. All you need is a divider set to some programmable integer value - a little more complicated than dividing by 2, but certainly achievable with a bit of standard logic. And fwiw, 28800 and 14400 are "standard" baud rates - I used to own a dial-up modem which would connect at these speeds. \$\endgroup\$
    – brhans
    Commented Oct 16, 2019 at 21:29
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    \$\begingroup\$ And the 768 from @brhans is 256 * 3 -- so divide by 3, then by 256. Or if you're building a typical receiver that oversamples by a factor of 16, divide by 48 (or 3 and then 16). \$\endgroup\$
    – TimWescott
    Commented Oct 16, 2019 at 21:33
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    \$\begingroup\$ I designed a UART in early 1976 before MOT released their chip. It used the same 16x clock for Start bit sync and centre sample +/- 1/16 clock initial phase error, which is standard for RS232 . You dont start with the baud clock, you start with the 38400 and use a UART chip or use any other clk/ divider N that results in 16x clk to generate center quasi-sync 1x clock for each byte. \$\endgroup\$ Commented Oct 16, 2019 at 22:21

1 Answer 1


If you have a high enough original clock, you'll be close enough then you divide down even if it's not an exact integer ratio.

For example, to divide a 50MHz clock down to 9600Hz, you ideally need a ratio of \$5208.\overline{3}\$. But that's not an integer ratio so I just use 5208 instead. I'm only off by 1/3 of 20ns (period of a 50MHz cycle) every 9600Hz period. That's within 64ppm even though I'm off by a whopping 1/3 of a digit in the integer ratio because the original frequency is so high that each clock pulse is worth that much less.

Even with a 4MHz, oscillator you're within 0.16%.


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