If an 8,500 transistor Z80 microprocessor were manfactured using 7nm transistors rather than 1970s era 6µm, how small would it be?

  • \$\begingroup\$ This looks looks like it may be a homework question. Can you provide a context? Will it have any integrated memory? \$\endgroup\$ – Caleb Reister Oct 16 '19 at 23:34
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    \$\begingroup\$ @Caleb It's definitely not a homework question. I was just musing what we (humans) could theoretically build with current technology for biomedical purposes. Something like this is the closest I could find: phonearena.com/news/… And that was over 6 years ago... \$\endgroup\$ – Peter Oct 16 '19 at 23:40
  • \$\begingroup\$ You could probably swallow an original Z80 die (~3.5mm²), though I wouldn't recommend doing so. It also depends on whether you plan on having integrated memory. The ARM processor you linked to has both SRAM and flash. \$\endgroup\$ – Caleb Reister Oct 16 '19 at 23:49

Not counting the pad ring, it would use approximately \$\left(\frac{7}{6000}\right)^2 = 1.36 \times 10^{-6}\$ the area.

The original die was 3545×3350 µm, or 11.8 mm2. Even if you converted it to CMOS, roughly doubling the number of transistors, the core logic would be about 1/400,000 this size, or about 30 square microns.

If you divide the total chip area of the original by the number of transistors, you get about 1400 square microns, or a box about 37.5×37.5 microns. This accounts for not only the size of the transistor, but also its "share" of the chip infrastructure (power distribution, interconnects, isolation, etc.). I'm making the simplifying assumption that all of this scales linearly with minimum feature size, allocating a box of about 44×44 nm to each transistor.

As a standalone chip, it probably wouldn't be much smaller than the original, because of the perimeter required by the pads. A modern wire bonder can handle pads on a 100 µm pitch, so to get 40 pads (leaving the corners empty) would require a die of about 1200×1200 µm, or about 1/8 the area.


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