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I have a main buck DCDC 5V that feeds to five different LDOs(3.3V). To create power sequencing, I would like to use a resistor and a capacitor at the input of the enable pin of each LDOs and by changing the value of R and C, introduce enable delay. The input to the LDO's enable pin will be tied to the 5V rail. What are the pros and the cons of using this method to introduce enable delay? Thank you

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  • \$\begingroup\$ if the Enable pin has hysteresis, then go ahead with it. \$\endgroup\$ – analogsystemsrf Oct 17 at 3:03
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5 ICL's can mitigate the surge current. Did you want to do power down sequencing too? Another solution may be a ring Johnson counter with an enable input. But LDO's are usually low current so a low ESR intermediate bulk cap is all usually needed with DC OK logic signal if critical.

The cons to RC controlled logic std logic are variations in slope RC tolerances , spacing and logic input threshold variations unless sharing same chip.

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It's kind of a half-a** approach compared to proper supply sequencing - consider what may happen if there are brief power interruptions of various durations- can you make the circuit fail to properly sequence-- probably. And what discharges the capacitors- probably some parasitic path within the regulators that is not well controlled.

Maybe you don't really care if it always starts up properly and the user can just switch it off and on again (and no harm will occur to the user or the circuit), but that would never fly in many kinds of products where it is expected to work every time.

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