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From Nexperia data sheetI have a couple of designs using 74HC595BQ-Q100,115 shift registers. Some are using the SO-16 package, some the DHVQFN16. Some have five shift registers, some have three. ALL have a significant noise spike when the data is loaded to the output register. I am completely sure that it's not the update itself. Series resistors limit the rise and fall times of the control signals to values that are slow but within the chip data sheet, and if I disable the output update, the noise does not happen even though I'm re-writing the shift register.

I've gone as far as internal engineers at Nexperia who confirm that the SR itself is causing the noise "oscillating during update". The footprints for both packages don't support getting the bypass caps any closer than I currently am, and I've tried bypasses from 1nF to 10uF, multiple caps.. I can't afford the room for X2Y caps here, and no guarantee that that would solve the problem.

The outputs go to an LED display through series resistors. All that is within package ratings, and I can't change the output current demand. I have seen that the noise goes away if I completely disconnect the outputs, but even 4.7K resistors in series produce almost as much noise as the 68 ohm resistors currently used.

The frequency of interest is in the 100's of kHz so shielding materials work particularly poorly down there. I've tried Mu metal, Finemet, flexible ferrite.. Nothing makes a noticeable change.

As you can see, I'm forcing all the current in both VCC and GND paths to go through the capacitor pads, not even allowing a "T" connection.

I've actually toyed with the idea of using a programmed ARM here, I can get one in a very similar package, internal clock, and even at the same price! However that's a bit of a project with no guarantee of success.

typical PCB layout

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  • \$\begingroup\$ Comments are not for extended discussion; this conversation has been moved to chat. Any conclusions reached should be edited back into the question and/or any answer(s). \$\endgroup\$ – Dave Tweed Oct 17 at 23:49
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I would attempt to lower the ESL of the high frequency signals as it is inductance that blocks high frequency.

I would double the vias of the decoupling capacitor to take the via inductance in half. I would also use an X2Y capacitor with much lower ESL (and ESR), they short high frequencies out much better than normal capacitors. I would also try an locate the capacitor closer to the ground of the shift register as the current has a longer path to take to get outside of the part, this also adds a small amount of parasitics.

Parasitic inductance on Vcc is not noticed as much as ground inductance.

It also appears that you might have some copper that might turn into a radiator.

Make sure you have a good continuous ground plane on one of the layers (which I'm sure you do, just not apparent in your post)

enter image description here
Source: https://johansondielectrics.com/downloads/x2y-filter-and-decoupling-capacitors.pdf

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  • \$\begingroup\$ I'm familiar with X2Y caps, and they are used elsewhere in this design. But as I said I don't have room for them and their via farms here. :) I could probably move the bypass over to the ground side of the chip, and run VCC from the cap to the VCC pin, but it would involve vias, which of course add inductance. \$\endgroup\$ – user103218 Oct 17 at 20:21
  • \$\begingroup\$ @user103218 Vias are not the evil you believe them to be. They outperform traces when used properly: electronics.stackexchange.com/questions/436583/… electronics.stackexchange.com/questions/443323/… \$\endgroup\$ – DKNguyen Oct 17 at 20:36
  • \$\begingroup\$ Thinking on moving the cap to the other end of the chip, doesn't that equate to just rotating the chip 180 degrees on the current layout? The loop area would be practically identical. \$\endgroup\$ – user103218 Oct 17 at 20:39
  • \$\begingroup\$ Thanks for the discussion so far. I will be in the hospital tomorrow, so I won't be able to respond, but hopefully I can get back to this this weekend and worst case monday. I just didn't want anyone to think I was ignoring them. I have to go for the day in a few mins, so again thanks so far, and see you again soon! \$\endgroup\$ – user103218 Oct 17 at 20:45
  • \$\begingroup\$ @user103218 Are you referring to the 2nd image in the first link? If so, you might be looking at the wrong schematic in that image. You want the bottom schematic, not the top. it says you need two caps, one to the left and one to the right of the IC (or I suppose under it works too as long as it is on either side of the Vcc-GND pin centerline). \$\endgroup\$ – DKNguyen Oct 17 at 20:51
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You must define the noise spectrum by risetime, pulsewidth at 50%V.

Relevant                Irrelevant
--------------          ----------------
trace nH/mm             signal frequency
trace pF/mm             
coplanar vs vertical
thin prepreg 5V-0 for C 
controlled Z 66 Ohm +/-
2W/L ceramic caps* Murata
Decoupling SRF, PRF and  ESR optmized to match spike spectral bandwidth
  f-3dB bw = 0.35/Tr (10~90%V)

There are over 50 types of decoupling caps.

Do you have the wrong caps?

  • like XR% 10uF 0.1uF or
  • or Murata 2W/L type 1nF // 1uf low ESL/ESR ceramic or tant.

*ESR Controlled Type Low ESL Capacitors Equipped with Anti-resonance Control Function Ref MURATA

You may be picking up false noise.

Do you have the proper test method?

  • proper coax AC couple test points to 50 Ohm terminated 200MHz DSO for Vdd-Vss noise. X2Y is the proper FEEDTHRU cap, and NOT a decoupling cap.
  • proper 200MHz 10:1 calibrated probes using only <= 6mm spring clips to signal and ground to calibrated DSO

Do you have the best layout?

  • Insufficient layout details stack-up and trace Zo
    • loop current area and coupling pF to crosstalk,
  • can use adjacent vias to increase W/L ratio and reduce ESL.
  • excessive load capacitance from copper pour vs gnd thieve/guard tracks.
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