I've written a set of "bit-bang" software routines for the PIC18F2620 device. These routines work well for reading and writing 24LC256 EEPROM and DS1307 RTCC devices for the most part. (I wrote this set of routines after spending a hair-tearing week trying to get C18 HW I2C to consistently work).
I am now writing verification (V&V) tests for this set of routines and am experiencing intermittent failures when writing longer sequences of data to the 24LC256 (> 40 bytes). My system has a 2mSec timer running (TIMER0) high priority, and a USART receive interrupt on low priority. I am beginning to suspect that the TIMER0 interrupt is leaving a Master-write sequence hanging too long during an interrupt, and the slave 24LC256 is giving up. Since there is no such thing as clock stretching for the master I believe I may have to start disabling interrupts during Master I2C transactions (from I2C_Start through I2C_Stop). I am leary of writing code where an interrupt is disabled in one routine and with hopes that it will always be properly re-enabled in another routine. (kind of a malloc/free situation).
Before adding these enable-disable interrupt changes I want to ask if others in this forum have had to deal with similar situations, and how they were handled.