Suppose I'm an experienced analog designer, e.g., RF, power electronics, ADC.

How does choosing a circuit topology fit into the overall workflow for a typical work assignment? I imagine my manager will be responsible for a larger system, like a whole RF to digital pipeline, and will ask me to do a specific component like a power converter or an oscillator. I imagine the workflow for my oscillator is something like,

1) Using some amount of intuition and experience, choose a circuit topology given the requirements.

2) Perform calculations to estimate critical component values, using scripts to optimize.

3) Repeat 1 and 2 if a given circuit topology wasn't a good choice.

4) Tape-out or some other form of pre-fabrication, etc. etc.

In practice, how does #1 play out? Do designers generally have a bunch memorized and ready off the top of their heads, with one or two go-to's to try first? How often do they need to learn new topologies, or develop new ones entirely? When multiple topologies might work, what metrics might be used to consider which to choose first? What resources or references do they use to look for new topologies when familiar ones don't meet their requirements? How might this work-flow vary between RF, power, low-frequency, embedded vs IC, etc.? Examples or case-studies would be really appreciated.

I ask in part where, coming from a mostly coursework background, usually topology is fixed and "design" just involves analyzing circuits to choose their parameters. The open-endedness of "build an oscillator with given specs", when there's dozens of feasible oscillators out in the wild, sounds overwhelming, so I want to understand the heuristics and thinking that are used to deal with this.

  • 1
    \$\begingroup\$ suppose you design Flip Flops; you should have 10 --25 topologies for FFs, and fully understand the merits of each, across bipolar and CMOS, CML etc. Ditto for Low Noise RF Amplifiers. And for oscillators. and Audio Power Amplifiers. And for ADCs. Hunt for, collect, understand (napkin design and simulators) various choices. \$\endgroup\$ Oct 19, 2019 at 3:16

2 Answers 2


How does 1 play out?

I spend a portion of my time researching circuits. A good engineer is also a good researcher, they know how to find information. There are many sources, books, research papers, manufacturers app notes to look for circuits that have already been built. This gives one an idea of how to build circuits by understanding each component of the design.

An engineer can take a design and deconstruct it to find out what all the pieces do.

If I want to build an op amp, then I need to understand how to build amplifiers on a transistor level and how they affect the input to output range.

If I want to build an RF signal chain, I gather a list of requirements (like input specs, output specs, costs ect), then go find a circuit/design that will do that (if there is one that fits my requirements).

2) uses paper, excel and circuit simulators like spice to verify the design will fit the requirements.

One example is I am always looking for low noise temperature sensors, thermistors don't cut it anymore, I look around for new technologies, I found one that uses lasers. I contacted the research group, they asked for more money than I had avalible, and that means we stick with thermistors (until that tech gets commercialized)

  • \$\begingroup\$ @ voltage spike After reading your profile, I think you may be interested in the SCE tool at robustcircuitdesign.com , which has various interferers built in (and editable if you wish), the interference energy coupled into the PCB traces. \$\endgroup\$ Oct 19, 2019 at 3:13
  • \$\begingroup\$ @analogsystemsrf that's a cool tool \$\endgroup\$
    – Voltage Spike
    Oct 20, 2019 at 1:58

Often, for board-level design one engineer will be responsible for an entire board. If it's complicated, or if it has a mix of critical digital and analog components, or if it's got an FPGA on it, more may get involved. But aside from that:

Typically, yes, a designer will have topologies in their heads, waiting to be fit to a purpose. But we generally try to keep up with what other people are using, and to some extent or other, we're generally ready to try new ones at need to meet novel specifications.

When multiple topologies will work, I usually analyze what I think are the top contenders for the specifications I think need to be met (which often go beyond the stated specifications, or which are themselves derived from the board-level specifications).

On the flip side of the coin, there are people out there who cling to just a few topologies, and aren't willing to be moved from them. In spite of what non-engineers think, there's a lot of personality involved in board (or, presumably, chip) design.


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