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I have searched the statement; MOS worst-case gate capacitance in various forms but no avail.

Keep in mind I'm a student. The course I am taking has no reference material. With note slides with pictures and formulas.

The only "formulas" that are provided for gate capacitance are:

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There is no text on what does a worst case gate capacitance per unit area means. Yet there is a homework question on it. There was no mention of it in class.

What does it mean? And how do you judge it is worst-case?

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  • \$\begingroup\$ A large gate capacitance will cause a FET to switch more slowly and increase switching loss. I would assume the "worst case" gate capacitance is the largest value the transistor can have. \$\endgroup\$ – PICyPICyPICy Oct 18 at 21:03
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    \$\begingroup\$ "The course I am taking has no reference material." You should seriously consider better quality courses! \$\endgroup\$ – JYelton Oct 18 at 21:05
  • \$\begingroup\$ Also need to show the transistor model to see where Cj and Ceq is \$\endgroup\$ – Voltage Spike Oct 18 at 21:17
  • \$\begingroup\$ In general, "worst case" means "the worst it can get" -- which means you need to know what worse is. In the case of gate capacitance, that's bigger -- circuit designers would love to get their hands on FETs with zero-capacitance gates. \$\endgroup\$ – TimWescott Oct 18 at 21:28
  • \$\begingroup\$ i think of a data sheet's min and max and typical specs for a mosfet; worst case would be max. \$\endgroup\$ – dandavis Oct 18 at 21:34
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The worst case gate capacitance is simply the max. gate capacitance specified in its datasheet. The highest value is considered the worst because higher means slower to switch on/off from the same drive circuit.

This maximum value will allow for variations in material properties and temperature.

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