I have coded a simple signed 4 bit adder. It doesn't have any carry in or carry out so it easily overflows. Below you can see my code.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity four_bit_adder_simple is port( A, B : in std_logic_vector(3 downto 0); Sum : out std_logic_vector(3 downto 0)); end four_bit_adder_simple; architecture signed_impl of four_bit_adder_simple is begin sum <= std_logic_vector(signed(A) + signed(B)); end signed_impl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity four_bit_adder_tester is port( SW : in std_logic_vector(7 downto 0); LEDR : out std_logic_vector(3 downto 0)); end four_bit_adder_tester; architecture tester_impl of four_bit_adder_tester is begin i1: entity work.four_bit_adder_simple(signed_impl) port map( A => SW(3 downto 0), B => SW(7 downto 4), Sum => LEDR(3 downto 0) ); end architecture;
How can I add a carry-in and a carry-out by using the resize function to change the bit size of the vectors before adding them together?