An AD ADA4622-1 with LFCSP8 Package shows as Thermal Specification a "2 Layer Board with 2x2 Vias".

What do this exactly means?

It is a pcb for the exposed pad pin with 4 vias distributed as a 2x2 square array, in a 2 layer board?

Anyway, where are those "Layer JEDEC Boards" drawings or specs?

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The datasheet shows the thermal resistance for different packages on different mounting setups: 1 layer PCB without vias, 2 layer PCB without vias, 2 layer PCB without vias, etc.

Because there are thousands ways to measure thermal resistance under another thousand different conditions the datasheet specifies which standard has been used to measure the thermal resistance:

Thermal impedance simulated values are based on a JEDEC thermal test board. See JEDEC JESD51.

When using a 2-layer PCB as described in JEDEC JESD51 with vias placed like the picture shown below, the thermal resistance for the 8-lead LFSCP package is 55°C/W.

Make sure to connect these vias to the correct power plane as per datasheet's note:

Exposed Pad. It is recommended to connect the exposed pad to the V+ pin.

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A thermal via with 1:1 ratio of perimeter to height, in 1 ounce / squarefoot PCB foil (which is 35 micron thick, or 1.4mils) and the via plating also done to 35 microns, has 70 degree Centigrade temperature difference for each watt of heat flowing thru that via.

If the perimeter/height ratio is 2:1, expect 35 degree Centigrade/watt temperature difference.

If the perimeter/height ratio is 4:1, expect 17 degree Centigrade/watt temperature difference.

Again, this is for 35 micron plating inside the via.


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