I'm trying to make a 4 bit adder with carry in & out, but I am having trouble converting Cin (Carry-in) to the type std_logic_vector when summing Sum and Cin together below in the architecture. Do you have any idea how i can make these types fit so that I can perform arithmetic on them together?
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity four_bit_adder_simple is port( A, B : in std_logic_vector(3 downto 0); Cin : in std_logic; Sum : out std_logic_vector(3 downto 0); Cout : out std_logic); end four_bit_adder_simple; architecture unsigned_impl of four_bit_adder_simple is signal total : std_logic_vector(4 downto 0); begin Sum <= std_logic_vector(resize(unsigned(A),5) + resize(unsigned(B),5)); total <= Sum + Cin; Cout <= total(4); end unsigned_impl;
EDIT: It was an error that I made Cout a 2 bit std_logic_vector. It should just have been a simple std_logic.