# VHDL: Convert std_logic to std_logic_vector

I'm trying to make a 4 bit adder with carry in & out, but I am having trouble converting Cin (Carry-in) to the type std_logic_vector when summing Sum and Cin together below in the architecture. Do you have any idea how i can make these types fit so that I can perform arithmetic on them together?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

port(
A, B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
Sum : out std_logic_vector(3 downto 0);
Cout : out std_logic);

signal total : std_logic_vector(4 downto 0);
begin
Sum <= std_logic_vector(resize(unsigned(A),5) + resize(unsigned(B),5));
total <= Sum + Cin;
Cout <= total(4);
end unsigned_impl;


EDIT: It was an error that I made Cout a 2 bit std_logic_vector. It should just have been a simple std_logic.

• Cout is 2 bits wide, which is odd... You are possibly missitg the fact that an array aggregate with one member can't use positional association. So use named association. (0 => Cin) is a 1 bit SLV. – Brian Drummond Oct 19 '19 at 18:45
• @BrianDrummond You need to add Cin, not concatenate it. So the total line is wrong. – user110971 Oct 19 '19 at 18:53
• As @BrianDrummond says, Cout looks like it should be corrected to a std_logic output. – TonyM Oct 19 '19 at 18:54
• If Cout should be an SLV, it should be a 1 bit SLV, e.g. (0 downto 0). And I was merely converting Cin to a SLV. Who mentioned concatenation? – Brian Drummond Oct 19 '19 at 18:58
• Re: your edit. You still have an error. Your output Sum doesn't take Cin into account. – Blair Fonville Oct 19 '19 at 21:06

You need to cast cin to an unsigned, then add it in.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Port ( a    : in  std_logic_vector(3 downto 0);
b    : in  std_logic_vector(3 downto 0);
cin  : in  std_logic;
sum  : out std_logic_vector (3 downto 0);
cout : out std_logic );

signal total : std_logic_vector(4 downto 0);
begin

total <= std_logic_vector(resize(unsigned(a),5) + resize(unsigned(b),5) + unsigned'('0'&cin));
sum   <= total(3 downto 0);
cout  <= total(4);

end Behavioral;


You'll end up with this:

Note that resize returns an unsigned here.

• Thanks, it seems to work now! – user234430 Oct 19 '19 at 21:31
• To simplify the code above, most type conversion/casting can be avoided by simply giving signals and ports the appropriate numeric type in the first place. – scary_jeff Oct 23 '19 at 8:11

The following is a simplification of your design that meets all the requirements and compiles in VHDL-93 onwards. It uses std_logic_unsigned rather than numeric_std. (Forgive the style changes, automatic when I typed and tested it.)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

port(
A                             : in  std_logic_vector( 3 downto  0);
B                             : in  std_logic_vector( 3 downto  0);
C_IN                          : in  std_logic;
SUM                           : out std_logic_vector( 3 downto  0);
C_OUT                         : out std_logic
);

signal total                    : std_logic_vector( 4 downto  0);

begin

total  <=  ('0' & A) + ('0' & B) + ("0000" & C_IN);

SUM    <=  total( 3 downto  0);
C_OUT  <=  total( 4);

end architecture RTL;