I have designed a buck converter (poorly) and have been getting terrible noise. I made a post here where I was given suggestions on how to do a proper layout for my buck converter. This post also lists my schematic, board layout, and external components used.

But when probing around more with my oscilliscope I noticed that the output of the buck converter that goes into the inductor doesn't look quite right. I compared it to a buck converter that I designed that I believe is operating well. enter image description here

It seems I have this terrible "ringing" on the output, and I do not believe this is correct. I was wondering if anyone has any insight as to what is happening, and solutions to relieve it if not listed in the previous post. Thank you all for your help!

  • \$\begingroup\$ How do you know that it's not right? What do you expect to see? How much load current there is? What if you put more load on it, like 1A total? \$\endgroup\$
    – Justme
    Commented Oct 19, 2019 at 18:41

1 Answer 1


What you're seeing is a normal switch node waveform in discontinuous mode.

The inductor current increases during the switch ON time, then ramps down during the OFF time. If the inductor current reaches zero before the next ON time, the inductor will ring with the capacitances on the switch node. This is the sinusoidal damped ringing you see on the switch node. Image from here:

enter image description here

If you increase the load on the output you will see the converter transition to continuous mode and the waveform will look like a square wave without the ringing, since the inductor current will never reach zero image:

enter image description here

  • \$\begingroup\$ I understand that the ringing is due to energy transfer back and forth between an inductance and capacitance. What I don't understand is which inductance and capacitance. The inductance, I'm assuming, is referring to the primary series inductor. How about the capacitance. Is this referring to the output capacitor, in parallel with the load, or the parasitic capacitance within the switching FET, when in a high impedance state? I'm assuming the latter, is this correct? \$\endgroup\$
    – mrbean
    Commented Sep 4, 2020 at 20:21
  • 1
    \$\begingroup\$ @mrbean Correct, it's the sum total of the parasitic capacitances on the switch node. (FET output capacitance, layout capacitance and if non-synchronous then the diode capacitance.) \$\endgroup\$
    – John D
    Commented Sep 4, 2020 at 20:37

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