Consider the following simple buck converter

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It consists of an NMOS input device, a diode, inductor and capacitor and a load. If we are limited to a gate voltage on the NMOS device of 12 volts peak-to-peak, what is the maximum input voltage that we would be able to use with this limitation? Assume a threshold voltage of 3V.Neglect NMOS on-resistance

Here's what I think:

For an NMOS $$V_{GS} >V_{TH}$$ $$V_G - V_S > V_{TH}$$ Neglecting the NMOS on-resistance, we get: $$V_G - V_{in} > V_{TH}$$

Since we have a 12V-p-p signal at the gate, the maximum gate voltage is 6V. Substiuiting this, along with our 3V threshold voltage, I get $$6V-V_{in} > 3V$$ $$-V_{in} > -3V$$ $$V_{in} < 3V$$

Is this correct?

  • 4
    \$\begingroup\$ The problem is under-specified. With that limitation, as stated, I would design a gate driver that drove the gate voltage relative to the source, and kept it at \$0 \le V_{GS} \le 12\mathrm{V}\$. Then the maximum input voltage would be limited by the maximum \$V_{DS}\$ of the FET, which is not stated in the problem. \$\endgroup\$ – TimWescott Oct 19 at 19:52
  • \$\begingroup\$ Yes, this is underspecified. It's like asking how big of a vehicle can you steer using a steering wheel 1.5 feet in diameter. It's not really related and there are plenty of straightforward ways around the loose relationship that does exist. \$\endgroup\$ – DKNguyen Oct 19 at 19:54
  • \$\begingroup\$ This is a lab issue I was having. The gate voltage is fixed at 12V-p-p, the input voltage was variable between 7 and 13V, however I was unable to drive an input voltage higher than approx 10V due to the FET turning off. Hence, why I'm doing this calculation, to see where that 10V limit was coming from. My calculation for some reason is telling me the input voltage has a maximum of 3V, so that's my confusion. The VDS of the MOSFET is in the 100's of Vs. \$\endgroup\$ – AlfroJang80 Oct 19 at 19:57
  • \$\begingroup\$ Show us the gate drive circuit. Do you know what a high side floating gate driver is? Do you realize the MOSFET only cares about the voltage between gate and source? Not gate and ground? The MOSFET cannot see and does not care what the voltage between gate and ground is. Think about what happens if you apply a voltage to the gate which is ground referenced and the voltage at the source pin changes as the MOSFET tries to conduct. What happens to Vgs? \$\endgroup\$ – DKNguyen Oct 19 at 20:06
  • \$\begingroup\$ Since we have a 12V-p-p signal at the gate, the maximum gate voltage is 6V. I'm missing the logic. Why wouldn't the maximum gate voltage be 12V, the max of this 12V-p-p signal at the gate? Could you please explain? \$\endgroup\$ – Huisman Oct 19 at 20:19

The problem is the voltage you are applying to the MOSFET gate is relative to ground, but the MOSFET doesn't care about the voltage between gate and ground. It cares about the voltage between gate and source.

As the MOSFET tries to conduct, the voltage at the source (relative to ground) rises, while the voltage at the gate (relative to ground) remains the same.This decreases the voltage between gate and source preventing the MOSFET from turning on further. You have an source-follower and not a switch.

You need to drive the MOSFET gate voltage with a voltage that is referenced relative to the source-pin voltage. Use a floating gate driver.


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