2
\$\begingroup\$

When calculating the input-referred noise and filtering to a 24-bit sigma-delta ADC (MCP3561), I hit a roadblock. Knowing the noise spectrum density (nV/sqrt(Hz)) of a signal noise source, like thermal noise, the noise in uVrms (microvolt root mean square) is calculated using the bandwidth of the signal. The latter number should be the noise floor that determines the effective resolution. Therefore I need to know what bandwidth (frequency span) applies in my scenario:

The ADC will do internal oversampling to form a single one-shot reading. The signal is from a thermistor where the bias power will be pulsed at 10 Hz for the duration of ADC, hence the signal itself is assumed constant for the measurement period and I suppose the signal frequency is 10 Hz. But 0-10 Hz can't reasonably be the frequency span to calculate noise from, as the ADC is inactive most of the time.

Is the frequency span from 0 to the oversampled sampling time (in the kHz range, but just one sample)?

Or is the frequency span from 0 to the internal ADC sampling rate (in the MHz range)? But I read that higher ADC speeds reduce the noise problem, which isn't consistent with this idea. And while the ADC runs at 4.9 MHz, the sampling time for each oversampling level is specified as 3x the expected (for example OSR=128 takes 78 us = 12.8 kHz = 4.9 MHz / (3 * 128)) so even the internal frequency is unclear to me.

It's also easy to imagine even higher noise frequencies affecting the measurement, but maybe any high-frequency noise is filtered in the ADC and included in the ADC datasheet ENOB? Maybe some Nyquist limit is involved.

The goal is to understand the practical measurement resolution under different Vref values and oversampling levels, and to optimize the filters. It seems to me that the slow signal may be filtered until thermal noise is the limit, but to know this I need the thermal noise of the signal as uVrms.

\$\endgroup\$
  • \$\begingroup\$ The main idea behind oversampling is that you filter the unwanted frequencies digitally after the sampling. Hence the noise in that frequency range is attenuated. This is also further complicated by the noise shaping in the sigma-delta modulation. I also think you are getting confused between analog noise (thermal) and quantization noise. Oversampling only helps with quantization noise, because it is spread in the interval [-Fs/2, Fs/2]. With that in mind, you should edit your question. It is not clear exactly what you are asking. \$\endgroup\$ – user110971 Oct 21 '19 at 11:09
  • \$\begingroup\$ I have edited the question to clarify. As I understand it, quantization noise is specified in the datasheet so I don't need to calculate that. I need to know what is "that frequency range" where oversampling attenuates. "Unwanted frequencies" is anything above 10 Hz, which isn't helpful to calculate the noise power. I don't see why oversampling would helps with quantization noise and not input noise. \$\endgroup\$ – Anders Petersson Oct 21 '19 at 17:54
  • \$\begingroup\$ To see why oversampling does not affect the input noise consider an ideal ADC having infinite sampling rate and infinite ENOB. It will perfectly reconstruct the input signal. Hence there will be no quantization noise. However it will not do anything to the input noise. This is what you would expect to see. The sole purpose of an ADC is to faithfully reconstruct the input analog signal in the digital domain. It cannot distinguish between input signal and input noise. It all looks the same to an ADC. \$\endgroup\$ – user110971 Oct 21 '19 at 19:36
  • \$\begingroup\$ You also say the power of the thermistor will be pulses at 10 Hz. Does that mean a duty cycle of 0.5? The pulsing of the power will introduce a rect windowing effect. So you’ll get the thermistor signal that you would get with the power always on convolved with a sinc window in the frequency domain. If you assume the signal is DC, as you have done, you’ll get a Dirac delta convolved with a sinc, which yields just the sinc centered at the Dirac delta. Since the Dirac delta is at 0 Hz, you are left with just the sinc function. Then you’ll need to have some anti-aliasing filter. \$\endgroup\$ – user110971 Oct 21 '19 at 19:47
  • 1
    \$\begingroup\$ But there is an upper limit, set by the filter bandwidth. Keep in mind that the thermal noise on a capacitor is (kT / C)^0.5. Hence the low pass anti-aliasing filter adds noise only in the passband. As for the cutoff frequency; it should be as low as possible, but high enough for the filter to settle in a reasonable time. Look at the step response of the filter. It can take a surprising amount of time to settle to within 24 ENOB. \$\endgroup\$ – user110971 Oct 21 '19 at 21:37
2
\$\begingroup\$

In any non-josephson-junction ADC, you will have analog comparators; their bandwidth likely will set the noise floor.

How to estimate the noise of the Comparator? simply use the input FET gate capacitance.

Using sqrt(K * T /C), the math behind switched-cap-sampling-noise, you'll find a 10pF capacitor produces 20 microVolts RMS noise. And a (more likely to get the C_gate_oxide value) 1pF will produce 20uVrms * sqrt(10pf/1pf) or 20uV * 3.16 = 63 microVolts RMS.

The over-sampling behavior has the effect of reducing the 63uV RMS to a value suitable, such as 2uV, for a 24-bit ADC.

One thing you may find interesting is the digitization of a 5uVPP sinusoid, or any well-described just-a-few-quanta input. Will the ADC produce the properly-binned code density? And how can we tell, in the face of 63uV dithering?

\$\endgroup\$
  • \$\begingroup\$ I have confidence in Microchip to account in the datasheet for all noise sources internal to the ADC chip. The MCP3561 table 2-1 summarizes the noise performance of the chip. Naturally they can't foresee the noise in the signal and Vref, hence I need to understand what input noise frequencies that will have an effect on the measurements when not using continuous ADC mode. \$\endgroup\$ – Anders Petersson Oct 21 '19 at 17:58
  • \$\begingroup\$ how clean will your VREF be? not having read the datasheet (yet), I suggest you proceed with a steady-state mindset. Some flicker (aka 1/F) noise phenomena, coming from low-frequency trapped-charges, will depend on how long the bias-voltages are applied. So I'd not worry about that. You should be aware of self-heating as an error source; the opamps and comparators inside the 24-bit ADC may or may not change behavior using the 100 microSeconds of initial silicon die heating after power-up. \$\endgroup\$ – analogsystemsrf Oct 22 '19 at 10:31
  • \$\begingroup\$ Thanks. I will filter VREF too, with the assumption that noise on VREF is just as bad as signal noise. I'll watch out for IC self-heating too. \$\endgroup\$ – Anders Petersson Oct 22 '19 at 21:52
  • \$\begingroup\$ How will you slit the Ground Plane, to better reduce the I * R voltage between the ADC and the Sensor? or to keep V = L * dI/dT induced voltages in the Vin+ and the Vin- traces? if a mutual inductance exists between the GND plane and the Vin+ trace, of size 10nanoHenry, and a current flows along GND path with 0.1 amp/100nanosecond (from a switching regulator), the Vinduce = 1e-8 H * 10^+6 amp/sec == 0.01 volts. So one of your challenges is to STEER currents away from the Vin+ and Vin- traces, and the underlying GND plane. \$\endgroup\$ – analogsystemsrf Oct 23 '19 at 4:06
  • \$\begingroup\$ Thanks, that calculation was helpful. I added two slits. The ADC buffer is at the edge of the ground plane with the thermistor 45-50 mm out connected by Vin+/Vin- mostly on top of an extending strip of GND. It might be vulnerable to 5.8GHz wifi but I could even spray the signal path with conductive coating for an impromptu extra GND layer. \$\endgroup\$ – Anders Petersson Oct 23 '19 at 17:33

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.