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I have a question about parasitic inductances. Let's take the figure below as an example, a DPT circuit is shown here. I have added an inductor (parasitic loop inductance). I would like to have a closer look at the switching characteristics of transistors. Should an inductor also be added before and after the diode as well as between diode and MOSFET in order to consider the parasitic effects of the PCB? Or is it possible to keep the parasitic inductances so low (few nH) that they have hardly any effect on the transient processes when designing such a PCB? enter image description here

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  • \$\begingroup\$ I use the estimate of 25 nanoHenries per inch, or 10nH/centimeter. Width will cause variation, wider produces slightly lower inductance, by a logarithm of the width. And a piece of metal over a plane will reduce the inductance about 5:1. Thus a wire in air will be (approximately) 25nH, but that same wire close to a plane (VDD or GND) will be (approximately) 5nH. \$\endgroup\$ – analogsystemsrf Oct 21 '19 at 10:11
  • \$\begingroup\$ Thanks a lot! :)) \$\endgroup\$ – Noah Oct 25 '19 at 10:15

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