I have an Altera Cyclone IV FPGA (for ie) and my question is: is it possible a raw programming of the FPGA? Is it possible to set "manually" the gates for making experiments?

Thank you

  • \$\begingroup\$ programming without using Verilog/VHDL ? \$\endgroup\$ – Mitu Raj Oct 21 at 10:21
  • \$\begingroup\$ An FPGA contains a lot of 'logic blocks' that the synthesizer connects based on how you describe the hardware in your code. Even if it's just an 'AND' gate the interconnection of the blocks will be such that it produces the result of an AND gate whether that be by a look up table or multiplexer. So I don't think it's possible to manually set the gates \$\endgroup\$ – Simeon R Oct 21 at 10:33
  • \$\begingroup\$ @MituRaj uhm this is an interesting question. Yes, I'm interested to some way for creating an output file for a FPGA without using a hardware description programming language. But this because I'm interested about a documentation for "raw fpga programming", but I'm pretty sure that this depends by the constructor. \$\endgroup\$ – rikicecchi Oct 21 at 11:40
  • \$\begingroup\$ @SimeonR thank you \$\endgroup\$ – rikicecchi Oct 21 at 11:41
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    \$\begingroup\$ Not for that FPGA where too much is secret, but there is a part (IIRC from Lattice) where sufficient information has become available, more realistically enabling open source tools. \$\endgroup\$ – Chris Stratton Oct 21 at 14:05

Surely if you were able to fully comprehend and become knowledgeable of all of the following factors regarding a particular FPGA it would be possible to hand craft programming files for the device.

  1. Detailed binary format requirements for FPGA programming file.
  2. Mapping of how programmable cell states of programming file map to features of the FPGA.
  3. Detailed understanding of the protocol used to load a programming file into the FPGA.
  4. Thorough understanding of the logic cell structure of the FPGA and how it maps to programmable cells.
  5. Full comprehension of how internal routing functions work and how connectivity is related to programmable cells.
  6. Good knowledge of how the I/O cells work and how they bus into the interconnect matrix of the FPGA.
  7. Understanding clocking requirements of the FPGA and how this relates to power on initialization.
  8. Detailed understanding of how the global clock distribution network in the FPGA is routed and connected to other internal elements.
  9. Good comprehension of the global reset domains of the FPGA and how they are routed and connected to internal elements.
  10. An understanding of how hard coded macro cells of the FPGA work including repeaters, buffer memory, PLL, DPLL, SERDES and any other things the manufacturer has chosen to throw into the mixing pot.

I have probably left out a basket full of additional details that would be very important to be familiar with that would play into making successful hand coded designs. Timing and delay compensation come to mind here.

It should become obvious very quickly that there is a reason that FPGA vendors provide development tools to cover almost all of these details. Using a recognized standard description language to describe the function intended for an FPGA design makes your intellectual property portable to almost any FPGA. Trying to understand what you have asked about regarding hand crafting a programming file is easily 20 to 30 times the work and would only be usable on one or two devices in some specific FPGA family. I suggest that your energy would be much more well spent becoming an expert at usage of the standardized description language.

If part of your curiosity is a drive toward becoming a designer/creator of FPGA components themselves then I suggest that you start by focusing on one particular aspect of the technology and learn that. If you had a job at one of the FPGA houses you would be part of a large team that includes dozens of skillsets that all come together to produce the FPGA products and tools that you will find in the market today.

  • \$\begingroup\$ It's not just that it's complicated, but that the industry has developed in a direction where a lot of the necessary information for most parts is kept intentionally secret. \$\endgroup\$ – Chris Stratton Oct 21 at 14:52
  • \$\begingroup\$ @ChrisStratton good point. Anyway, FPGAs have to face off with the "open source community" sooner or later, but for sure the market of these devices is advantaged by an oligopoly condition for a long time. Anyway, these conditions are also justified by the (I hope) big investment that companies like Altera or Xilinx had to do... reddit.com/r/FPGA/comments/a5pzs5/… \$\endgroup\$ – rikicecchi Oct 21 at 17:39

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