There's a lot of post on here about MOSFETs and ESD sensitivity. But whenever the general question is asked, people always go straight to the gate and how sensitive it is.

I've developed an LED driver board, with common-annode LEDs connected. Therefore, I have the drain of the low-side N-Channel MOSFETs exposed - and lots of them. The board has 52 of these exposed:


simulate this circuit – Schematic created using CircuitLab

Since I have so many, I really don't want to have to place 30V+ TVS diodes on every single output. If I have no choice, I guess I will. But I was just wondering - since they do have a parasitic body diode, is there any chance the drain will be okay - at least for EMC testing - by itself?

  • 1
    \$\begingroup\$ Does the drain provide a path for electrons to reach the atoms-thick gate? Yes it does. Though not so easy as from the source to the gate. But y'know...static is thousands of volts and even the MOSFET source-drain can only withstand 1500V if specifically designed for it, and the static doesn't even have to go all the way from source to drain to reach the gate. \$\endgroup\$
    – DKNguyen
    Commented Oct 21, 2019 at 22:12
  • \$\begingroup\$ FETs are extremely vulnerable to ESD. The datasheet can provide proof of that. BJTs are generally susceptible to ESD but it is still vulnerable. \$\endgroup\$
    – user103380
    Commented Oct 21, 2019 at 22:17
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    \$\begingroup\$ You should do it anyway. As well as ESD you could also have inductive kickback due to long wires. \$\endgroup\$ Commented Oct 21, 2019 at 23:39
  • \$\begingroup\$ -1 Most power MOSFETs are specified as being "avalanche rated" for overvoltage spikes on their drain terminal, as long as the source is grounded. For example, the common IRFB3607 MOSFET is rated for 120 millijoules, around 10x the maximum energy of a typical human ESD event. The only time you'd have to worry about ESD to the drain is if the miller capacitance (gate-drain / gate-source) was enough to raise the gate voltage above its maximum rating. I've never seen any power MOSFET with these characteristics. \$\endgroup\$ Commented Jan 27, 2021 at 19:09

3 Answers 3


Yes, mosfets drains are sensitive to ESD. If you look at the Vds spec in the datasheet, it cannot be exceeded (for the IRF530, it's 100V), even for short amounts of time.

ESD over-voltage conditions can reach thousands of volts. To prevent failure of the mosfet, install ESD protection. One way to do this would be to use a TVS diode that limits the voltage on the drain to less than 100V (maybe 50V would be best).

If its a choice between placing a TVS diode or replacing the mosfet (or having an intermittent mosfet that behaves unpredictably, a TVS diode would be a better choice.

There are a few mosfets, such as the DMN61D8LQ that have ESD/diode protection built in to the part, however, there might not be one with the specs needed for your design. If needed TVS diodes could be placed on the outside of a mosfet to give it ESD protection or additional ESD protection (if the ESD rating of a mosfet isn't high enough).

enter image description here

Source: https://www.diodes.com/assets/Datasheets/DMN61D8LQ.pdf

If the LED's are connected to the outside world and are touchable by humans (or moving cables can generate thousands of volts on them if moving across a surface), then the mosfets need to be protected.

  • 2
    \$\begingroup\$ Alright, I suspected as such - just good to hear it from another person. Thanks. The sources are all grounded, and the gate has no exposure to the outside world. So I'll place a 30V TVS from the drain to source, and hope for the best. Cheers! \$\endgroup\$
    – DSWG
    Commented Oct 22, 2019 at 0:45

MOSFETs are notably ESD sensitive on account of the high impedance of the insulated gate.

The gate is insulated from the body of the transistor by a layer of silicon dioxide, which forms a capacitor between the gate metallisation and the body of the MOSFET.

This input capacitance is called Ciss. https://techweb.rohm.com/knowledge/si/s-si/03-s-si/4873#:~:text=Ciss%20is%20the%20input%20capacitance%2C%20and%20is%20the,as%20a%20whole%2C%20as%20seen%20from%20the%20input

Any charge, Q, finding its way onto Ciss develops a voltage Q/Ciss. If this voltage exceeds the breakdown voltage of the silicon dioxide layer, damage will result.

The other pins are not any more ESD sensitive than other components in general, so you don't need to be especially concerned about the drain connection.

  • \$\begingroup\$ Generally Ciss is much higher than any other capacitances in the MOSFET, notably the gate-drain (AKA "Miller") charge that could cause gate overvoltage due to a voltage spike on the drain. \$\endgroup\$ Commented Jan 27, 2021 at 19:16

Let me play the devil's advocate against the reply of Voltage Spike. Therefore, this reply is intended to be challenged or debunked if it is not accurate.

Yes, mosfets drains are sensitive to ESD. If you look at the Vds spec in the datasheet, it cannot be exceeded (for the IRF530, it's 100V), even for short amounts of time.

I don't think this is accurate. Besides Vds ratings, the datasheets also present the avalanche rating, which specifically applies to situations when the Vds rating is violated. I will use the already mentioned IRF530 FET (https://www.vishay.com/docs/91019/91019.pdf) to demonstrate my idea. The datasheet shows a test schematic in the Figure 12a, where a coil is first allowed to charge up through the enabled MOSFET. Then, the MOSFET is turned off and the coil current is forced through the D-S, which will clearly violate the VDS rating and the energy stored in the coil gets dissipated in the body diode in the avalanche breakdown mode of operation.

Avalanche breakdown is the same physical phenomenon as the one employed in the high-voltage Zener / TVS diodes. Therefore, I argue that the body diode itself acts as a TVS and then, the avalanche energy must be respected to prevent thermal damage to the device.

Avalanche breakdown exhibits a very steep V-A characteristics, i.e. very small differential resistance, once it happens. Given that that standard ESD models have relatively large series resistance, I would argue that the voltage is effectively clamped by the body diode.

Example: An 8kV HBM is modeled by a 100pF capacitor with a 1.5kR series resistance. The energy stored in this model is E = 0.5 * 100pF * (8kV)^2 = 3.2mJ. The avalanche energy of IRF530 is 69mJ (more than 20-times as much). So even if the whole energy of the ESD was dissipated in the FET, it is very much safe (note that a significant amount of the energy will be dissipated in the HBM series resistance). Additionally, the avalanche energy is tested with the coil charged to 14A, which is much larger compared to the maximum current delivered by the 8kV HBM (8kV / 1.5kR = 5.33A), which means that even the peak current and power dissipation are considerably lower during the ESD event than the ones used in product testing.

  • \$\begingroup\$ Sounds convincing. Is there any restriction regarding pulse width for the avalanche energy ? Avalanche breakdown rather than the zener effect is in fact usually what 'zener diodes' do (certainly much above 5 volts). en.wikipedia.org/wiki/Zener_effect \$\endgroup\$ Commented Mar 26, 2021 at 2:39

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