Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned).
The Xilinx Timing Closure User Guide indicates that the tools will take care of the inter-clock domain path requirements, so reading a single bit in the slow clock is safe. My question is: will the tools also make sure that all the bits of in the bus will be synchronised to the same slow clock edge, or is there a risk that some bits may arrive on different cycles without any further constraints?