Clock domain crossing of a bus between related clocks

Question

Imagine I want to transfer a bus from a fast clock (i.e., 100MHz) to a slower clock (50MHz). The clocks are related (come from the same MMCM, phase aligned).

The Xilinx Timing Closure User Guide indicates that the tools will take care of the inter-clock domain path requirements, so reading a single bit in the slow clock is safe. My question is: will the tools also make sure that all the bits of in the bus will be synchronised to the same slow clock edge, or is there a risk that some bits may arrive on different cycles without any further constraints?

Answer 1

Given that both fast clock and slow clock are synchronous, properly multi-path constraining these paths ensure that there are no metastability conditions. But it still cannot address the other problem we have while transferring data from fast to slow clock : Data Loss.

Consider a situation, where the source flop is generating the data at a higher frequency. And, the destination flop is getting triggered by a slower clock. In this case, before the destination flop captures a data, the source clock would have launched the next data. Thus, for fast to slow crossing, there is always a risk that only intermediate data might get captured, and, several data might get lost. In order to prevent this data loss, it is important to turn off data generation till the capture clock has been able to sample the data.

Handshaking or FIFO mechanisms are usually incorporated to address this issue.

Read thru chapter 4 and 7 of this book for more insight