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In my PCB, there are two GND polygons (1 & 2) which are connected to the same GND plane. The only way I was able to connect them was through vias as shown below:

enter image description here

I realized that two current paths current could happen (the desired path and undesired path). However after looking at it further, I think that the undesired path is not likely because electrons will be flowing from GND polygon 2 to GND polygon 1 through the via trace. These flowing electrons will repel the electrons flowing in GND polygon 1, leading me to believe that this layout is ok. Is this the case, or should I be concerned about the undesired path/ other issues I may be overlooking?

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  • \$\begingroup\$ If this path is undesired, then why not remove the link between the polygons? \$\endgroup\$
    – Hearth
    Oct 22, 2019 at 16:24
  • \$\begingroup\$ If they aren't connected GND polygon 2 is then a ground island. \$\endgroup\$
    – abjf4t8
    Oct 22, 2019 at 16:25
  • \$\begingroup\$ Then where is the current going through it? If this is the only connection, there can't be any alternate path that the current would take involving it. \$\endgroup\$
    – Hearth
    Oct 22, 2019 at 16:26
  • \$\begingroup\$ Current source in polygon 2 is from a microcontroller \$\endgroup\$
    – abjf4t8
    Oct 22, 2019 at 16:31
  • \$\begingroup\$ If this trace is your only link between the two polygons, then any ground current that goes between the two will necessarily go along the link. \$\endgroup\$
    – Hearth
    Oct 22, 2019 at 16:33

2 Answers 2

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Since you have a 2 layer board, add a Gnd plane to the bottom layer and connect both pads using Vias to the Gnd plane.

In my designs, I make everything that is not a trace or a component pad part of the Gnd planes on the top & bottom layers, and let them connect by either moving traces a little to let Gnd plane connect by themselves, or by adding vias to connect the various islands that are left after routing is done.

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  • \$\begingroup\$ Do you add extra vias to connect the top and bottom GND plane as well? \$\endgroup\$
    – abjf4t8
    Oct 22, 2019 at 16:35
  • \$\begingroup\$ Yes I do. Get as much Gnd coverage as I can. When I was still in industry, we had 16 layer boards, with whole layers dedicated to Power and Gnd. Now as a hobbyist, I limit designs to 2 layers for cost, and keep as much Gnd intact as I can, with nice wide traces for power connections. The more current that is expected, the wider the trace. \$\endgroup\$
    – CrossRoads
    Oct 22, 2019 at 16:39
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Is this the case, or should I be concerned about the undesired path/ other issues I may be overlooking?

The best way to determine if ground stitching will be a problem is to calculate the resistance of the trace and the vias.

For example: If the trace above were about 100mils long and 12mils wide, this would be about 4mΩ of resistance. The vias will also add another 2-3mΩ combined (assuming 10mil vias).

This is about 7mΩ of resistance.

Look at how much common mode voltage this can create:

1mA would be 7uV of voltage 10mA would be 70uV of voltage 100mA would be 0.7mV of voltage

Which is tolerable for most analog and digital designs. There can be problems

The same can be done for the inductance of the trace and vias. I'd estimate that the vias would contribute 1.5nH max each and the trace would be about the same.

If you had a 5-10mΩ resistor with a 5-10nH inductor and a 0.1uF or 1uF capacitor, it will have a resonance point in the 1 to 10MHz range, which could be a problem for EMI.

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