I am designing a PCB to use with the AS7265x sensors. The datasheet states, on page 51:

In order to prevent interference, avoid trace routing feedthroughs with exposure directly under the AS7265x devices.

Would it be fine to use a 4-layer PCB with a middle layer for a GND pour and another with VDD? I would expect the pours to shield the ICs from any routes traced on the bottom layer (ICs on top).

Datasheet: https://ams.com/documents/20143/36005/AS7265x_DS000612_1-00.pdf/08051c8a-a7f6-6231-7993-2d3fe0bf38b8

  • \$\begingroup\$ I would read it as: do not put any copper under the IC. Figure 63 also shows the route away Vsupply and GND. I didnt go into detail of the datasheet, but for e.g. magnetic driven IC's (current conduction) copper under the IC influences the working f the IC \$\endgroup\$ – Huisman Oct 22 '19 at 19:20
  • \$\begingroup\$ I see. So even GND in another layer would possibly cause interference... :/ That makes my project a bit more constrained. Thanks anyway! :) \$\endgroup\$ – Lurosset Oct 22 '19 at 19:54
  • \$\begingroup\$ No, it may cause interference, it may not. You need to go into details how the IC works. Check also application notes, see how the layout is done for evaluation boards (if they exist), etc \$\endgroup\$ – Huisman Oct 22 '19 at 20:02

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