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This is a fairly specialised topic about DAC capacitor arrays for SAR ADCs. In particular, this charge-redistribution DAC is of a split-capacitor type.

I'm having some difficulty understanding the operation of it. The paper I reading is https://ieeexplore.ieee.org/document/4140585

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Here's my understanding:

  • In the "sampling" block in the flow-chart above, both the main subarray of capacitors and MSB subarray get ground on their positive top plates and get Vin on their negative bottom plates. Thus, both capacitors charge up such that a voltage difference of -Vin is present across them (top plate (+) - negative plate)
  • We move to the "Start Bit-Cycling" block in the flow-chart. All capacitors have Vin on their negative plates. The bottom (negative plates) of the MSB sub-array capacitors only are now connected to Vref.Thus, the top plate of these sub-array capacitors will change by (Vref-Vin). Charge redistrbution occurs since top plates of main-array is at 0. The capacitors now settle at (Vref-Vin)/2? I'm getting confused here. What happens exactly after bottom plates of sub-array capacitors are connected to Vref?
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Instead of one C for the MSB stage of the SAR, there are duplicate half-size C caps to reduce the switching energy losses. The mirror split Cap and SAR are top and bottom.

They report 37% lower switching energy was optimally achieved without increasing the C storage area at 500Mbps.

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