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I've got a variable pulse wave (that looks like a square wave) ranging from 5Hz to 60Hz.

The peak voltage is 5V. I'm trying to design a low pass filter that effectively gives the average voltage as a DC output but am struggling to get an acceptably flat output, it currently fluctuates 0.5V. I've got 100n and 470n capacitors on hand so they are ideally the values I'd like to use. Can also run through up to 4 op amps filters if that would improve the result.

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    \$\begingroup\$ Start by defining "acceptably flat". \$\endgroup\$
    – Eugene Sh.
    Oct 24, 2019 at 20:27
  • \$\begingroup\$ I would rectify and then filter it. Or use a good RMS chip. I would think that just filtering it would lose whatever information it contained. With a bipolar power supply the LMC660 can do a .1Hz low pass filter in a single stage, but all you get at the output s effectively DC. \$\endgroup\$
    – GB - AE7OO
    Oct 24, 2019 at 20:28
  • \$\begingroup\$ Take a look at the AD630 .analog.com/en/products/ad630.html It would do your job with the addition of a LPF afterwards. \$\endgroup\$
    – GB - AE7OO
    Oct 24, 2019 at 20:32
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    \$\begingroup\$ Show us what you've tried so far, and in addition to "acceptably flat", tell us how fast the filter needs to respond. \$\endgroup\$
    – TimWescott
    Oct 24, 2019 at 20:34
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    \$\begingroup\$ If it’s a square wave with peak voltage 5 volts then a perfect average filter always produces 2.5 volts. Because the result is always 2.5 volts, why do you need to derive a flat signal of 2.5 volts when you know the answer. \$\endgroup\$
    – Andy aka
    Oct 25, 2019 at 9:42

1 Answer 1

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I need to make some assumptions on ambiguous "specs".

Your amplitude jitter is 0.5/5V, which maybe Vpp or Vp.

  • let's assume that was Vpp so you have 10% jitter and you indicate that's unacceptable. But what is acceptable?

    • and at what f? Obviously the jitter in amplitude reduces with rising f.

Goal: measure Vdc (avg) <<10% jitter pulse 5Hz to 60Hz approx 5Vpp input variable amplitude (0-Vpk) and duty cycle (d.c.) nominal 50%, no extreme limit, yet. TBD

One method is to have a true integrator in one cycle create the result voltage and assume f does not change rapidly or < 1% per cycle. This is called an Integrate and Dump method or IDC often used in DMM ADC's for high noise immunity.

We know a simple LPF regardless of the order 1st or 4 more LPF's added (9th order) will always add delay or latency to the Vdc avg and that's also undesireable and unspecified.

So let's go with the IDC approach that uses the duty cycle and Vpeak voltage, where the product is the Vavg, DC steady result, regardless of the frequency.

Design motus operandi:

Using signal polarity relative to the midpoint, and edges , control an Integrator with sample & hold to integrate the positive pulse up and negative or 0V pulse down to achieve the integrated average voltage * period. Since the frequency is required to equalize time and thus a flat constant equal voltage a pulse at 5 Hz requires 10 pulses at 50 Hz to yield the same scaled result.

This result will be a perfect constant result at the slowest pulse rate of 5 Hz by design choice in 200ms with perhaps 0.1% ripple between the results of a dual S&H between two consecutive samples.

Gain control to prevent saturation and NPO ceramic or film caps only for the S&H are essential to avoid hysteresis, tolerance and acoustic errors.

Good luck with your specs for latency and ripple tolerance errors.

Mine are: 200ms and 0.1%

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