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I am trying to make a 32-bit register using 32 negative edge trigerred D F/F. Here is the verilog code for D F/F:

module dff(q,d,clk,reset);
    input d,clk,reset;
    output q;
    reg q;
    initial
        q<=1'b0;
    always @(negedge clk)
    begin
        if(~reset)
            q<=d;
        else
            q<=1'b0;
    end
endmodule

Here is the code for 32-bit register:

module reg_32bit(q,d,clk,reset);
    input [31:0] d;
    input clk,reset;
    output [31:0] q;
    genvar j;
    generate for(j=0;j<32;j=j+1)
                begin: reg_loop
                dff d1(q[j],d[j],clk,reset);
                end
    endgenerate
endmodule

Now, I expect that when I include the module reg_32bit in another module and try to read the register using q, then I should get all 0's initially. But when I try to do so, I get all x's instead.

What am I missing here?

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  • \$\begingroup\$ 1/ You have not told us what you do with the reset signal. You have a synchronous reset. Nothing wrong with that but it won't work unless you also have a clock. 2/ Your if is the wrong way around. \$\endgroup\$ – Oldfart Oct 26 '19 at 13:14
  • \$\begingroup\$ @Oldfart I don't want to use reset signal. As soon as I include this module into another, I want the register to have value all 0's without resetting the register. \$\endgroup\$ – Vipin Baswan Oct 26 '19 at 13:40
  • \$\begingroup\$ In that case you are at the mercy of the FPGA manufacturer. Most set the contents of register to zero, but I never rely in that. \$\endgroup\$ – Oldfart Oct 26 '19 at 13:52
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Initializing a register in this way is implementation dependent. It will work in some FPGAs that support a global reset at power up, but in general you should expect a flip-flop to have an unknown state when power is first applied. If your application requires an initial state for the flip-flops you should add an explicit reset to your design. Since you haven't told us the circumstances where you see this behavior we can't give a specific answer.

By the way, I think there is an error in your first if...else block. Check the order of the statements.

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  • \$\begingroup\$ That's a valid concern for hardware, sure, but "x" is likely an output of HDL simulation, not hardware running the synthesized result. \$\endgroup\$ – Chris Stratton Oct 26 '19 at 20:09

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