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I'm designing a smart socket that will route 240V AC Live and Neutral to a voltage regulator and also to a relay that will control the current flow. Due to the limited space, it will be easier to route the live wire on the top layer and neutral on the bottom layer as shown in the diagram below where the red track is AC Live and blue is AC Neutral. enter image description here

The PCB is two layers with a thickness of 1.6mm. Will there be any problem routing it this way? Will it create a voltage potential or capacitance of any type? Secondly, the relay can handle up to 5A, hence the tracks should be able to handle 5A too. Based on an online PCB trace calculator, the trace must have a width of 2.77mm which is quite hard to fit in the limited space. If I leave the traces to be exposed copper, can I then reduce the trace width?

[EDITED] This is the alternate PCB layout where it is on a single layer but as you can see it increases the track length quite significantly. enter image description here

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    \$\begingroup\$ It looks like you're planning on etching away all copper that isn't at trace. Don't do that. It's wasteful of etchant. Instead, use copper pours and connect them to ground. That also means that instead of your traces, you can make them into large pour areas to dissipate heat if there's nothing around the otherwise thin trace that it would encroach upon. \$\endgroup\$
    – DKNguyen
    Commented Oct 26, 2019 at 16:57
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    \$\begingroup\$ I'm actually using a PCB manufacturer to manufacturer the PCB where the cost of the copper will be the same regardless. Anyhow, I will be adding copper pours around it to increase the width but I'm concern if they get too close a spark may happen. \$\endgroup\$
    – Max
    Commented Oct 27, 2019 at 11:54
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    \$\begingroup\$ I'm talking from a larger view than just your wallet. It produces more chemical waste and takes longer to etch on their end. \$\endgroup\$
    – DKNguyen
    Commented Oct 27, 2019 at 17:55
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    \$\begingroup\$ @DKNguyen You're not really saving anything. The fab will use the same chemicals in the same amounts, it takes as much time to reliably etch a small gap as a large one from process - point of view. Copper voids can cause other issues on multi-layer boards but here we have quite little copper. \$\endgroup\$
    – Barleyman
    Commented Feb 13, 2023 at 23:42
  • \$\begingroup\$ @Barleyman It's still an environmental thing in any case. A really bare boards look ugly. \$\endgroup\$
    – DKNguyen
    Commented Feb 14, 2023 at 1:43

2 Answers 2

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There's usually very little difference in cost of 2-layer vs 1-layer and from technical point of view there's no issue since you're changing layer at TH pin. If you were to swap layer with vias it would be prudent to use several vias with a 5A track.

Track width guidelines are based on copper temperature rise and its no problem of having narrower copper at a pin if it then expands for most of the length as the heat will be dissipated at wide section.

As far as sparking goes, you generally want at least 2.5mm between line and neutral, also between line and PE as appropriate. Or any other unassociated copper.

I'd leave the solder resist alone, it's not a good/safe insulator but it's better than nothing. You may add copper pours to the tracks to maximize copper area if you like but soldering may become.. Challenging.

Don't forget neutral may be LIVE too!

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  • \$\begingroup\$ Oh, more than 3 years old. But it popped up on recents.. \$\endgroup\$
    – Barleyman
    Commented Feb 13, 2023 at 23:54
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I see still you can route such that there is no overlap.Also, you can keep P1 and P2 back to back such that P & N are next to each other and trace lengths can be minimum and width can be more.

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    \$\begingroup\$ Yes it is possible to route with no overlap as shown in the edited version but this can increase the length quite significantly. I can place P1 and P2 back to back but they are terminals blocks and placing them in that manner can make it hard for wiring later on. \$\endgroup\$
    – Max
    Commented Oct 27, 2019 at 11:58

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