I am new to Verilog. I need to find a way to modify setup/hold-time and clock to output delay timing parameters. Why I need this is to simulate a problem that changes the timing parameters with some value.
So, let's say in some reason the setup time of a flip flop has changes which resulted in incorrect behavior. But the designer has not considered such a timing change.
How can I modify the D-FF setup time in Verilog so that I can see the real-world problem?