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I am new to Verilog. I need to find a way to modify setup/hold-time and clock to output delay timing parameters. Why I need this is to simulate a problem that changes the timing parameters with some value.

So, let's say in some reason the setup time of a flip flop has changes which resulted in incorrect behavior. But the designer has not considered such a timing change.

How can I modify the D-FF setup time in Verilog so that I can see the real-world problem?

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  • \$\begingroup\$ What do you mean, "modify"? What tools and models are you currently using? Are you talking about simulation or static timing analysis? \$\endgroup\$ – Dave Tweed Oct 26 '19 at 18:38
  • \$\begingroup\$ "..so that I can see the real-world problem" I don't know what you want to do because set-up and hold time problems are well know. There is not much a simulation model you build yourself can teach you other then "something goes wrong" and it will always go wrong in the same way. Maybe you can elaborate a bit more about what you are trying to achieve. \$\endgroup\$ – Oldfart Oct 26 '19 at 19:56
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You will need to add delays to the clock and/or data signal to the specific flip-flop in question. Adding delay to the data input increases the effective setup time, while adding delay to the internal clock signal increases the effective hold time. The clock-to-q delay is controlled by delays added to the input clock as well as to the output q.

Of course, this assumes that you are specifying the behavior Verilog for the flip-flops yourself, rather than synthesizing to some target architecture. This technique will work for simulations only, not for static timing analysis.

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  • \$\begingroup\$ I have found a way of doing that in System Verilog link \$\endgroup\$ – Artur Petrosyan Oct 27 '19 at 6:25

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