There was an assignment as follows:

Design a two directional three-bit counter with the following functionality. the counter is changing its value on each positive edge of the clock. the counter's reset value is 0. After reset the counter is being incremented to value of decimal 4, then decremented back to 0. then incremented to 2, then decremented back to 0. and continue this defined whole sequence forever i.e.


After some days the verilog description was available as follows:

reg[3:0] internal_counter;

always @(posedge clk or negedge reset) begin
  if(!reset) internal_counter <= 3'd0;
  else if(internal_counter == 3'd11) internal_counter <= 3'd0;
  else internal_counter <= internal_counter + 3'd1;

always @(posedge clk or negedge reset)begin
  if(!reset) counter <= 3'd0;
  else if (((internal_counter > 3'd3) && (internal_counter > 3'd8)) || (internal_counter > 3'd9))
    counter <= counter - 3'd1;
    counter <= counter + 3'd1;

The problem is i could not understand the code? why there is an internal counter? Could you please kindly describe the above code? is this the only way to describe this kind of counters?

is the following FSM correct for this problem? Where

S0: increment until reach 4

S1: decrement until reach 0

S2: increment until reach 2

S3: decrement until reach 0


Then we can say:

always @(state or count) begin
S0: if(count < 3'd4)begin 
      count <= count +1; state = S0;
    else state = S1;
S1: if(count > 3'd0)begin 
      count <= count -1; state = S1;
    else state = S2;
S2: if(count < 3'd2)begin 
      count <= count + 1; state = S2;
    else state = S3;
S3: if(count > 3'd0)begin 
      count <= count - 1; state = S3;
    else state = S0;
default state = S0; 

Is this a correct approach?

  • \$\begingroup\$ "After some days the verilog description was available as follows:" You told us this was an assignment, and then you want to tell me the school has given you the solution? \$\endgroup\$ – Oldfart Oct 27 '19 at 16:41
  • \$\begingroup\$ Yes after the assignment due. The correct answer will be available. \$\endgroup\$ – engineer1155 Oct 27 '19 at 16:48
  • \$\begingroup\$ Sorry but I have to give you the standard reply for this question: Please realise that this is not a free design house, homework-answering service or an on-line technical encyclopedia, copied out to you on demand. People will help you take the next step if your question shows that you've done as much as you possibly could on your own - which your post doesn't, I'm afraid. (I personally think that code is awful. Given the assignment I would have used a four stage FSM with a counter.) \$\endgroup\$ – Oldfart Oct 27 '19 at 16:54
  • \$\begingroup\$ I just want some start points. because the only way came to my mind is to use successive if statements \$\endgroup\$ – engineer1155 Oct 27 '19 at 17:05
  • \$\begingroup\$ you have code with two successive IF (implied THEN) ELSEIF (implied THEN) ELSE ELSE. I suggest you parse this, re-write as nested IF THEN ELSE compound statements. The Verilog behavior is up to you. Do you see the (implied THEN)? \$\endgroup\$ – analogsystemsrf Oct 27 '19 at 17:26

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