There was an assignment as follows:
Design a two directional three-bit counter with the following functionality. the counter is changing its value on each positive edge of the clock. the counter's reset value is 0. After reset the counter is being incremented to value of decimal 4, then decremented back to 0. then incremented to 2, then decremented back to 0. and continue this defined whole sequence forever i.e.
After some days the verilog description was available as follows:
reg[2:0]counter; reg[3:0] internal_counter; always @(posedge clk or negedge reset) begin if(!reset) internal_counter <= 3'd0; else if(internal_counter == 3'd11) internal_counter <= 3'd0; else internal_counter <= internal_counter + 3'd1; end always @(posedge clk or negedge reset)begin if(!reset) counter <= 3'd0; else if (((internal_counter > 3'd3) && (internal_counter > 3'd8)) || (internal_counter > 3'd9)) counter <= counter - 3'd1; else counter <= counter + 3'd1; end
The problem is i could not understand the code? why there is an internal counter? Could you please kindly describe the above code? is this the only way to describe this kind of counters?
is the following FSM correct for this problem? Where
S0: increment until reach 4
S1: decrement until reach 0
S2: increment until reach 2
S3: decrement until reach 0
Then we can say:
always @(state or count) begin case(state) S0: if(count < 3'd4)begin count <= count +1; state = S0; end else state = S1; S1: if(count > 3'd0)begin count <= count -1; state = S1; end else state = S2; S2: if(count < 3'd2)begin count <= count + 1; state = S2; end else state = S3; S3: if(count > 3'd0)begin count <= count - 1; state = S3; end else state = S0; default state = S0; endcase end
Is this a correct approach?