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I have pasted a picture of a circuit. The transistors with an open circle on them are n-type. This meaning that a 0 voltage( or 0 input) activates the transistor. What I don’t understand is how to see the current running. More specifically the junctions between the transistor and the input A. Does the junction get influenced more by the 0 input or the 1 input and why?

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    \$\begingroup\$ this is a standard implementation of a NOR gate in CMOS: the top 2 devices are P_FETs in series; the bottom two in parallel are N_FETS. Resultant operation? "any high input causes a Low output" \$\endgroup\$ Commented Oct 28, 2019 at 7:49
  • \$\begingroup\$ On the picture you loaded (on the right side), it says "p-type". Consult a text book on "Digital Integrated Circuits" or "CMOS integrated circuits". \$\endgroup\$
    – Syed
    Commented Dec 7, 2021 at 5:56

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The transistors with an open circle on them are n-type.

This is very unusual. Usually we draw p-type FETs with a circle, and n-type FETs with no circle.

And your circuit is one that should have p-FETs where the devices with circles are drawn, and n-FETs where the devices without circles are drawn.

This meaning that a 0 voltage( or 0 input) activates the transistor.

This also describes p-channel MOSFETs, not n-channel.

What I don’t understand is how to see the current running.

You could try to simulate this on the Falstad simulator (Google it). It isn't a great simulator in a lot of ways, but it does provide a nice visualization of current flow for circuits like this.

More specifically the junctions between the transistor and the input A. Does the junction get influenced more by the 0 input or the 1 input and why?

Input A is attached to one n-FET and one p-FET.

The n-FET will be "on" (conducting current through its channel) when the input is high and "off" when the input is low. The p-FET will be "off" when the input is high and "on" when the input is low.

So both FETs will be controlled by whether the input is 1 or 0. There's no way to say that a 1 has more effect or a 0 has more effect.

But notice that the channels of the p-FETs are in series while the channels of the n-FETs are in parallel.

That means that both p-FETS must be "on" for the output to be pulled high, but having just one n-FET "on" can pull the output low.

Edit

In comments you said,

If you follow the wire leaving input A you see a junction where Input B meets input A. Which input is accepted and thus used in the topmost transistor and why?

The wires are not connected, they're just crossing over each other without connecting.

Connections are shown with a dot at the wire junction (circled in red, below). Unconnected crossings have no dot (circled blue):

enter image description here

Input A connects to and controls the upper p-FET and the right n-FET. Input B connects to and controls the lower p-FET and the left n-FET.

Inputs A and B are not connected to each other.

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  • \$\begingroup\$ Okay thank you for clarifying. But you did not answer my question. A wire must have current running through it or not yes? If you follow the wire leaving input A you see a junction where Input B meets input A. Which input is accepted and thus used in the topmost transistor and why? \$\endgroup\$ Commented Oct 28, 2019 at 18:37
  • \$\begingroup\$ Why isn’t as important. Just is it always true that at a junction a “0” input will always persist through a 1 input. \$\endgroup\$ Commented Oct 28, 2019 at 18:41
  • \$\begingroup\$ I don't see any junction where the wires for input A and input B are connected. Connected wires are signified by a dot where the wires cross. Where these wire cross there is no dot, therefore no connection. Also, the circuit would not work as intended if the wires were connected. \$\endgroup\$
    – The Photon
    Commented Oct 28, 2019 at 18:46
  • \$\begingroup\$ Oh I see. So the junction in question is really a splitting of the input A. \$\endgroup\$ Commented Oct 28, 2019 at 20:41
  • \$\begingroup\$ @DemarcusSales, I don't know which junction is the one in question, so I can't say. Input A is connected to one n-FET and one p-FET. So is Input B. Input A and input B are not connected to each other. \$\endgroup\$
    – The Photon
    Commented Oct 28, 2019 at 20:42
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That is basic CMOS logic. Most likely Wikipedia has an explanation for a CMOS NAND gate. Ideally in a static settig there is no current flowing, as inputs don't take current, there is no load on output, and there is no current flowing inside the chip as that would waste energy. The inputs turn transistors on and off. Any input being '1' will turn output transistor to ground voltage on, and any input being '0' will keep the path to supply voltage off.

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  • \$\begingroup\$ When I look at the junction between A and B I can’t tell which input the junction takes. Will 1 override 0 on the junction. Thus making the first transistor have a 1 outcome. Or will 0 override 1 giving the expected outcome \$\endgroup\$ Commented Oct 28, 2019 at 7:46

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