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I am trying to generate a dead time between two switching legs in the conventional full bridge inverter. However, by simply including the delay block for one pair of switches - just shifts the signal with the same duty ratio, resulting in cross conduction for the following sub interval. The duty ratio is generated by comparing the saw tooth signal against the reference sine wave. enter image description here

Any suggestions how to generate pulses without cross over? Thanks in advance.

UPDATE

I implemented dead time with the proposed RC and Differential Schmitt block. However, decided to stick with the DS. I have been trying to understand this very hard, but still no idea if the dead time is actually doing anything or not? From the graph below (top right) you can see how both pairs of switches are cross conducting even though drive signal clearly has a specified dead time (below). I also varied some of the SW parameters, but didn't see much of a difference apart from more graduate, softer transitions. Any idea if I should dwell on this further or can I just assume that they are "successfully" driven with a dead time?enter image description here

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  • \$\begingroup\$ You need to make the duty cycle shorter. \$\endgroup\$
    – winny
    Commented Oct 29, 2019 at 13:58
  • \$\begingroup\$ I understand that, but not sure how to do this appropriately. \$\endgroup\$
    – Rr Bb
    Commented Oct 29, 2019 at 14:21
  • \$\begingroup\$ Oh! You are generating it from the triangle wave. I usually cheat with controlled voltage sources directly. Many ways to do it! Try a Schmitt trigger and set the rise and fall times unevenly and feed that to a digital buffer? \$\endgroup\$
    – winny
    Commented Oct 29, 2019 at 14:41
  • \$\begingroup\$ As it is you have a 100 ns dead-time (glad you found the schematic helpful). If you need to check whether there is some, plot the gate signals. If you're plotting the voltages in the bridge (as I presume you did, since I can't know where your V(n002) is, if you don't label it) then you may get "cheated" by the uneven switching characteristic of the MOSFETs (the voltages and currents don't switch like an ideal switch, there are delays due to the physycal properties). \$\endgroup\$ Commented Dec 9, 2022 at 21:29

3 Answers 3

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Duty cycle shortener (winny's suggested name): -

enter image description here

The lower waveform in the picture above can be used for top-left and bottom-right switches. An inverted version of the middle waveform (use a NAND gate instead) can be used to activate top-right and bottom-left switches.

  • Choose logic gates that have schmitt trigger inputs.
  • Choose RC to give appropriate time delay in line with schmitt trigger input levels.
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    \$\begingroup\$ Perhaps I should trademark it! :-) \$\endgroup\$
    – winny
    Commented Oct 29, 2019 at 16:25
  • \$\begingroup\$ Thanks to both of you. However, I can not find AND or NAND with Schmitt trigger inputs. I can use a Schmitt-triggered buffer though, right? \$\endgroup\$
    – Rr Bb
    Commented Oct 29, 2019 at 16:36
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    \$\begingroup\$ 74xx132 springs to mind \$\endgroup\$
    – Andy aka
    Commented Oct 29, 2019 at 17:12
  • \$\begingroup\$ Thank you, I just updated the original post and asked another question. (Didn't want to generate another topic.) \$\endgroup\$
    – Rr Bb
    Commented Oct 30, 2019 at 13:37
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    \$\begingroup\$ It seems to me that you should have generated a new question because this new question seems to stand on its own and personally, I hate evolving questions and resist answering them unless they are quite related to the original. This isn't as far as I can tell and also, there could be a mess of answers such as mine answering the first question and somebody answering the second question and which answer would you choose to formally accept? HINT - look at the currents in the MOSFETs to inspect dead time. \$\endgroup\$
    – Andy aka
    Commented Oct 30, 2019 at 14:13
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I know that the post have been since quite long-time, but I came here during my search for a behavioral modelling for dead-time, such that I would avoid using spice models of gate-drivers which would slow down my test. However, I see that you already did it and your model works well. You were wondering why you cannot see the effect of dead-time because actually you have been looking at the wrong thing. Your waveform shown is just a measure of VDS of Q1 and Q2(I assume this because I don't know what is net N002, I assume it's the input DC source). You cannot examine the effect of dead-time using only VDS, because dead-time is used to prevent the shoot-through problem when you have two series MOSFETs turned ON at same time which open a path for huge current to flow from DC source to GND. You would have been able to examine the dead-time effect by showing the current going through S1 & S2, also during the dead-time the current goes through D1 or D2!

Anyway, I am including the waveform of my full-bridge circuit that does have dead-time, but there is no shoot-through current. Waveform for voltage and current in Q1 & Q2 in a full-bridge converter

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There is an alternative solution: use an LTC7060 (single PWM input) or LTC7061 (individual high/low inputs, adjustable dead time). This IC basically implements the (adjustable) dead time and since it's from ADI/Linear, a model comes with LTSpice.

Image from LTC7061 datsheet

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    \$\begingroup\$ Please provide a link or citation for the source of the graphic you copied into your answer. The policy for this cite is to provide attribution for any copied material. \$\endgroup\$ Commented Dec 9, 2022 at 16:27

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