In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that division of certain floats on certain processors became substantially slowed, as the instructor described, because the division needed to take place in microcode because of underflow.
Where in the instruction pipeline does microcode translation take place, and how does it fit into the N-stage pipeline as taught in undergrad coursework? Does microcode translation take place for all instructions, or only complex instructions?
To be concrete, let's focus on modern Intel architectures.