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In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that division of certain floats on certain processors became substantially slowed, as the instructor described, because the division needed to take place in microcode because of underflow.

Where in the instruction pipeline does microcode translation take place, and how does it fit into the N-stage pipeline as taught in undergrad coursework? Does microcode translation take place for all instructions, or only complex instructions?

To be concrete, let's focus on modern Intel architectures.

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  • \$\begingroup\$ Intel architectures (and x86 in general) don't correlate directly to the 5-stage RISC pipeline. They have extra stages everywhere for decoding to microcode, caching decoded instructions, reordering, branch prediction... the "classic" RISC pipeline isn't really used anymore, even by RISC-like processors, except perhaps in the microcontroller world. You can think of microcode as an internal, simpler ISA that wraps the external ISA. It's not RISC, because there are lots of instructions, but it's like RISC-inside-a-CISC. \$\endgroup\$ – anonymous Oct 30 '19 at 6:16
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    \$\begingroup\$ Thanks Jon Harper, I've edited the post to reflect the asker's (my) familiarity with >5 N-stage pipeline seen in modern chips. \$\endgroup\$ – Dragonsheep Oct 30 '19 at 7:22
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    \$\begingroup\$ This isn't enough for an answer, but I highly recommend Hannibal of Ars Technica's history on the Pentium Pro and other articles on later Intel chips. They do a really great deep dive on the stages of the pipeline, when translation occurs, and there are a series of followup articles on the Intel processors that came later, including how they differ (for example, there is one of the Pentium 4 and its weird micro-op cache). IIRC the articles are now combined into a book. \$\endgroup\$ – anonymous Oct 30 '19 at 9:14
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Instruction-to-instruction translation can take place anywhere between the (documented ISA machine code) instruction fetch unit and the microcode dispatch logic into the scheduling and (often these days, N-way) execution pipelines. “Code cracking.” Perhaps over or within several pipeline stages. Simple instructions map close to one-to-one. “Complex” or “non-RISC-like” instructions, one to possibly many. Thus, (documented ISA) instruction fetch and (different, implementation dependent) instruction dispatch are further decoupled in time (number of clock cycles per instruction or number of “instructions” per clock) as well as space (number of instructions fetched versus executed, and their bit widths).

Read more about computer architecture (history), as this was standard implementation practice in many (most?) computer systems designed between the IBM 360 and the Berkeley RISC, Stanford MIPS era. Except Cray. MC68000 even used more than just one level of translation.

Often done because processor logic and data path could be clocked faster than memory bandwidth. And with wildly varying ratios over an ISA family.

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