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I am using a QuadSPI interface in MPC5606S

Can someone help me how to arrive at the maximum and minimum clock freq of SPI and IO lines?

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Looks to me like Figure 49 suggests its determined by minimum values of Tf and Tr. So the absolute minimum clock period determined by that is 0.4 + 0.3 = 0.7ns, or about 1.4 Gigabits per second. That being said, the "typical" values in Table 65 indicate a more conservative bound would be 0.5 + 0.6 = 1.1ns, orabout 900 Megabits per second.

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  • \$\begingroup\$ Thank you. Before accepting the answer, just a small query, what is the maximum pin toggling frequency of the Microcontroller? Does the datasheet provide the value in different terminology? \$\endgroup\$
    – Newbie
    Oct 31 '19 at 13:27
  • \$\begingroup\$ Seems to me like the maximum operating frequency of the chip is 64MHz... which is probably is what actually limits your SPI frequency \$\endgroup\$
    – vicatcu
    Oct 31 '19 at 13:41
  • \$\begingroup\$ So, I can't run my QuadSPI clock at 900MHz as you calculated? If the maximum is only 64MHz, what's the point of the rise time and fall time being so low to provide 900MHz? \$\endgroup\$
    – Newbie
    Oct 31 '19 at 13:47
  • \$\begingroup\$ Can you please tell \$\endgroup\$
    – Newbie
    Oct 31 '19 at 14:02
  • \$\begingroup\$ @Newbie because its more convenient to make that way. slow edges means metastability and higher power consumption, and possibly more work to make the transistors have slower edges to. the same way a steel spoon is a lot stronger than it need to be when plastic spoons suffice. \$\endgroup\$
    – DKNguyen
    Oct 31 '19 at 14:02

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