# How must be the pull up resistor circuit connected to the driver input?

I have this circuit for getting 12V or 0V from external control signals. Signals will arrive by pin connector to my board. Switches will also be out of this board.

External control signal could be high Z or GND, depending on switch state.

I Would like to bring control signals (HZ/0V) from connector to the drivers: ULN2803.

• When input = HZ the idea is that driver output 0V, this is my proposal.
• So when input = GND --> driver output must be 12V.

This is what I need and this driver can achieve this behavior.

I can see how my first circuit stage do:

a) When D = HZ, current goes from vdd source to driver GND because it will be ON.

b) When D = 0, current goes from from vss to vdd source (being switch on, of course).

1) But I would like tu design the previous stage correctly and efficiently. Is it any better option for connecting the external control signals to the driver?

2) Someone told me about the need of buffers before driver. I'm asking if this circuit could really need some buffering devices and what kind of buffer could fit better here in this application.

• But are you aware that ULN2803 is just a Darlington Transistor Array? Which means that the "driver" output is an open collector type and the driver can only sink current (LOW state at the output, V_OL > 0.6V) (you will never get 12V at the driver output without pull-up resistor)? And how can a current once flow from VDD to GND and another time from VSS to VDS? Isn't the current always flow from Higher voltage to the lower voltage?
– G36
Oct 31, 2019 at 15:58
• How long is the wiring between the external board and this circuit? Oct 31, 2019 at 20:17

As I can understand, the goal is to "inverse" an external switch behaviors by own circuit. In THIS case:

Quite enough to debounce input switch using a shunt-to-ground capacitor. There is no significant reasons to place buffer here. Usage of Schmitt trigger, surely is a "best practice", but often is not applicable due to unacceptable complication of circuit.