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To charge a 4 cell Li-Ion battery pack, microchip have developped a circuit (board) that I am trying to understand, (the link for the PDF is here:https://www.microchip.com/developmenttools/ProductDetails/MCP1630RD-DDBK3)

The charger is built using a microcontroller and MCP1630V as an SMPS Contol Unit (see page 16/30 and 17/30).

The MCU feeds MCP1630V with PWM signal of Fs=500kHz. If we look closer to the circuit, we notice that FB and COMP pins of MCP1630V are short-circuited, which means that the internal error amplifier of MCP1630V is used as a buffer.

My questions are all about the circuits that are connected to Vref of MCP1630V.

We have an OPAMP referenced as U4:B used as a second order active low pass filter cascaded with a passive low pass filter composed of R32 and C21. The output of this third order low pass filter is connected to the inverting pin the OPAMP referenced as U4:A in the circuit. The non-inverting pin of U4:A is connected to:

1.the current sensing circuit of the battery (composed of R4 and R5).

2.VCC through R24.

My first question is, if we consider U4:A as an error amplifier (As it appears), what is the purpose to connect the inverting input of this OPAMP to the output of the 3rd order low pass filter and the non-inverting input to current sensing circuit of the battery?

Second, why have we connected THREE outputs (through R22, R19, R12) to Vref of MCP1630V? How does these outputs influence PWM output(Vext) of MCP1630V?

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My first question is if we consider U4:A as an error amplifier (As it appears), what is the purpose to connect the inverting input of this OPAMP to the output of the 3rd order low pass filter and the non-inverting input to current sensing circuit of the battery?

The IREF input (the input of the 2nd order LPF as you've said) comes from the MCU's RA6/AN5/PGC pin. Most likely that pin outputs a PWM signal to make a DAC in conjunction with the filter block (1). The voltage coming from that DAC is used as a reference to the Current Control Error Amplifier.

Second, why have we connected THREE outputs (through R22, R19, R12) to Vref of MCP1630V?

The control circuitry consists of 2 blocks (Error Amplifiers):

  • Voltage Control EA (VCEA): Managed by the error amplifier composed by U3:B and its surrounding components (R11, C9, C10, etc).

  • Current Control EA (CCEA): Managed by the error amplifier composed by, as I've already explained above, U4:B and its surrounding components.

The outputs of these error amplifiers are connected to the VREF pin of MCP1630 through equal resistors, R19 and R22, respectively. And this pin also tied to 2.5V through a 15k pull-up resistor, R12, to set its initial voltage.

how do these outputs influence PWM output(Vext) of MCP1630V?

First, let me put the block diagram of the MCP1630V:

![enter image description here

Second, the corresponding part of the circuit:

enter image description here

The block diagram of the MCP1630V in conjunction with the circuit diagram will help you to understand better how it works. Sorry, I don't have enough time to make a detailed explanation.

But here's a brief explanation:

As I have already stated above, the VREF pin of MCP1630 is tied to 2.5V through a 15k pull-up resistor, R12. And the outputs of the VCEA and CCEA are connected to this pin through equal resistors. Initially, VCEA's output is HI (5VDC) and CCEA's output is probably LO (0V). You can verify it from the schematic. So the initial voltage of the VREF pin is around 2.5VDC. It's obvious that the voltage at this pin controls the PWM output (Vext) and thus the output of the converter which is formed by ISL6207 and its surrounding components.

The CCEA and VCEA will try to keep the voltage at VREF pin at some level to adjust the PWM signal and regulate either the current or the voltage by trying to pull the VREF voltage LO or raise it to HI. Think of it as the operation of an OR gate: Whichever wins, it will regulate its input signal. For example, at unloaded state, CCEA does not work thus VCEA wins so the output voltage will be regulated.

Let me say this again: To understand how the circuit works, you do need to "read" the block diagram of MCP1630V.


(1) Fourier analysis of a PWM signal brings a duty-cycle-dependent DC component (i.e. mean voltage which is equal to duty cycle times peak voltage) and AC components (i.e. harmonics). The DC component can be varied by playing with the duty cycle, and we can get rid of the harmonics via RC filters. So we can build a non-precise DAC with PWM + RC filters. The more the cascaded RC filters, the closer to a pure DC we can get.

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    \$\begingroup\$ @luxinapado Look at the main converter carefully: If you look from left to right (i.e. the input to the left, the output to the right), the converter looks like a non-isolated buck converter: Q1 acts as a switch and Q2 acts as a flywheel diode. But if you look from right to left, the converter looks like a boost converter (don't see Q1). ... \$\endgroup\$ Nov 1 '19 at 22:20
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    \$\begingroup\$ ... If you want the converter to work as a constant-voltage buck (regulating VBULK) then you need to decrease the VREF. Similarly, if you want the converter to work as a constant-current boost (regulating current at VBAT side) then you need to increase VREF. VCEA and CCEA play with each other to maintain control over VREF voltage. That's why the circuit is called "Bi-directional Charger". ... \$\endgroup\$ Nov 1 '19 at 22:21
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    \$\begingroup\$ @luxinapado Final notes: If there's nothing connected to VBULK (i.e. neither a battery nor a voltage source) the converter will work as a constant-voltage SR (synchronous rectification) buck converter getting its input from the battery pack connected to J1. In this mode, VBULK will be regulated to around 6V (\$=2.5V \cdot (1 + R9/R14)\$). If at least 6.5VDC is applied to VBULK from a source then the converter will work as a constant-current boost converter getting its input from VBULK and regulating the charge current at VBAT side. \$\endgroup\$ Nov 1 '19 at 22:30
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    \$\begingroup\$ @luxinapado Look at MCP's block diagram and the latch's truth table. S input comes from the oscillator signal and R comes from the output of the comparator named Comp (FB and COMP pins are shorted in the circuit so EA becomes a buffer thus the inv input of the Comp is VREF). When the osc signal is high, if the Vref is greater than or equal to CS then the R will be low thus the \Q will be low. If the Vref is lower than CS then the \Q will be high regardless the state of the oscillator signal. How long the S and R inputs are kepth low or high determines the duty cycle. ... \$\endgroup\$ Dec 2 '19 at 5:21
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    \$\begingroup\$ @luxinapado ...Now look at the actual circuit. Suppose the J1 side is loaded and the ref voltage (IREF) is non-zero. The Vref pin comes from the output of U4A which is the controller for the current at J1 side. If the voltage drop induced by the current (hereinafter InputSignal) is higher than IREF then the Vref will be high. Since the CS pin will be low due to the Q3 when the osc signal is high, it's guaranteed the \Q will be high. If the osc signal is low (and thus S is low) then the CS pin will be high enough. So, if the Vref is higher than CS then R will be low and \Q will be \Qn.. \$\endgroup\$ Dec 2 '19 at 5:42

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