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Circuit diagram : JK Flip-flop

Will it remain in the state \$Q = Q-bar = 0\$ as the feedback given back will always be zero?

Will this lock the JK in this state as long as the \$V_cc\$ is connected?

Note: I have used the word initially, because doing it on a later stage probably won't affect the internal SR latch.

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That flip flop, as drawn, will lock in whatever state the outputs are in. Bearing in mind that the outputs must be the complement of each other. If both outputs are both 0 then the flip flop will almost immediately force one of them to a 1.

I don't know if you intended to draw the flipflop incorrectly but to get it to perform that truth table you must not swap the feedback connections over. That is to say feedback from an output should go to the same side input. The feedback connections are only swapped over on their way back to the inputs on a nand/nand jk flipflop.

EDIT

In the theoretical situation of both outputs being 0, it would mean both inputs of each nor gate were 0, forcing both outputs to 1. With a 1 on the nor inputs both outputs would be forced to 0 and in an ideal world the outputs would oscillate at high frequency between both being 0 and both being 1 for ever. Because the flipflop is not ideal, the gate delays are different to each other which means that the flipflop would settle with one output at 0 and the other output at 1. It would be impossible to predict which output would settle high and which output would settle low. With the incorrect feedback connections shown, the flipflop would then be locked in that state.

That type of jk flipflop should be clocked by a very short clock pulse (nanoseconds). If it is not then the outputs will oscillate in toggle mode, J=k=1 (even with the correct feedback connections) coming to rest in an indeterminate state.

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  • \$\begingroup\$ Will initially setting J=1 and K=0 and then toggling K to 1 preserve the state of the internal latch, as Q=0 will be given to the AND gate connected to K again? \$\endgroup\$ Nov 2 '19 at 14:33
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    \$\begingroup\$ With J=1 and K=1, Q=0 and Qbar =1, both inputs to the lower nor gate will be 0. Therefore Qbar stays at 1. With those incorrect feedback connections, the outputs will remain locked regardless of what the J&K inputs are. \$\endgroup\$
    – James
    Nov 2 '19 at 15:13
  • \$\begingroup\$ Until I turn J/Clk=0? As that will change the input to the sr latch to 0,0 \$\endgroup\$ Nov 2 '19 at 15:28
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    \$\begingroup\$ In that situation outputs from both 'and' gates is 0 as you say. Then upper nor gate has inputs of 0 & 1 so Q output stays unchanged at 0. Lower nor gate has inputs of 0 & 0 so Qbar stays unchanged at 1. \$\endgroup\$
    – James
    Nov 2 '19 at 16:50
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The output of the flip-flop depends on the previous output. When J=K=1, the output(Q) of the flip flop toggles. That is, if the previous output was 1, the output will now be 0 and vice versa.

The state of Q-bar is always opposite of state of Q.

Do verify my answer. You will be clear.

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  • \$\begingroup\$ Note: I have used the word initially, because doing it on a later stage probably won't affect the internal SR latch. \$\endgroup\$ Nov 2 '19 at 9:58
  • \$\begingroup\$ Q and Q-bar are just labels. Initially both of them will be low ~ 0 V. \$\endgroup\$ Nov 2 '19 at 9:59

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