That flip flop, as drawn, will lock in whatever state the outputs are in. Bearing in mind that the outputs must be the complement of each other. If both outputs are both 0 then the flip flop will almost immediately force one of them to a 1.
I don't know if you intended to draw the flipflop incorrectly but to get it to perform that truth table you must not swap the feedback connections over. That is to say feedback from an output should go to the same side input. The feedback connections are only swapped over on their way back to the inputs on a nand/nand jk flipflop.
In the theoretical situation of both outputs being 0, it would mean both inputs of each nor gate were 0, forcing both outputs to 1. With a 1 on the nor inputs both outputs would be forced to 0 and in an ideal world the outputs would oscillate at high frequency between both being 0 and both being 1 for ever. Because the flipflop is not ideal, the gate delays are different to each other which means that the flipflop would settle with one output at 0 and the other output at 1. It would be impossible to predict which output would settle high and which output would settle low. With the incorrect feedback connections shown, the flipflop would then be locked in that state.
That type of jk flipflop should be clocked by a very short clock pulse (nanoseconds). If it is not then the outputs will oscillate in toggle mode, J=k=1 (even with the correct feedback connections) coming to rest in an indeterminate state.