Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5):
If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus.
If I understand correctly, this causes every calculation to take a minimum of three cycles: Cycle #1: put the first operand on the bus, and copy it to a temporary register. Cycle #2: put the second operand on the bus, and copy it to a temporary register. Cycle #3: allow the ALU result on the bus.
This seems consistent with the timing tables (e.g. a register-register ADD is said to take exactly three clock cycles). (or not? I EDITed below)
However, this doesn't seem very efficient, and also, I saw other diagrams, like this one:
that also show the Flags as being sent to the same bus, which doesn't really make sense to me.
So - is this the actual physical implementation, or an abstraction, and actually the "ALU bus" consists of multiple 16-bit lines?
EDIT: I wrote: "This seems consistent with the timing tables (e.g. a register-register ADD is said to take exactly three clock cycles).". In second thought, I'm not sure that it's consistent, because the IP register also needs to be incremented, so with 3 cycles per ALU add, the entire ADD instruction should take 6 cycles...