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I have seen and worked with interfaces like SPI and I2C.

However, when I started to learn about DDR interface/communication protocol, I want to understand like how many lines, what are the important pins and how are the bits sent.

For ex, While learning about I2C and SPI interface, there are some websites that entirely talk about those two interfaces like each line and what it does and how are the bits sent and on.

But I was not able to find like this for DDR and PCIe interface. Can someone share if they know?

I researched that to understand DDR protocol we need to download the standard from JEDEC and for PCIe, it is PCI-SIG.

But it is very detailed and technical and tough for me to grasp while reading those PDFs.

Is there any other way to learn about those standards?

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    \$\begingroup\$ If you are referring to DDR (1,2,3,4) memory devices, then Micron has a wealth of application notes aimed at designers. \$\endgroup\$ Nov 4, 2019 at 13:55
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    \$\begingroup\$ To tack on to Peter Smith's hint. Also check the Xilinx DDR documentation. It has a TON of good PCB notes: xilinx.com/support/documentation-navigation/design-hubs/… \$\endgroup\$
    – pgvoorhees
    Nov 4, 2019 at 14:00

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is just a generic term meaning "double data rate", in which there is data associated with both edges of a reference clock, rather than just the rising edge or just the falling edge. It is normally associated with multi-bit buses, such as those used in memory chip interfaces. I have also encountered it in HD video interfaces.

PCIe does not use DDR. Instead, it uses a completely different signalling protocol known generically as — low-voltage differential signalling. In this kind of interface, each pair of wires carries a "lane" of data in very high speed serial form (5 Gbps and up), with an embedded clock. For higher data rates, multiple lanes can be used in parallel, but they are decoded individually and the data is merged into a single stream afterward.

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    \$\begingroup\$ Actually it is CML - link partner discovery is interesting, one might say :) \$\endgroup\$ Nov 4, 2019 at 14:14
  • \$\begingroup\$ Thanks. I googled the app notes for DDR and PCIe. NXP has one video for DDR Interface. Are there any university lectures or any seminars by manufacturers which explains the protocol with a sample design schematic. I think it would be beneficial if there was a video of a sample design schematic explaining the protocol and connections \$\endgroup\$
    – user220456
    Nov 5, 2019 at 2:26
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PCI Express is logically mapped the same way as PCI, but physically it is implemented as a number of point to point links. Due to the logically identical layout, the same base code to implement drivers is largely the same between the two types which is clearly very attractive from a driver perspective.

Each link has an associated Link Training Status and State Machine. (Xilinx Application Note).

The base link protocol (once the link between partners is established) is that there is constant electrical activity on the bus using line coded scrambled data even when there are no packets destined for the receiver (1). Versions 1 and 2 use the venerable 8b / 10b encoding and versions 3 and 4 use 128 bit / 130 bit encoding which reduces the line coding overhead significantly.

A scrambler is used to randomise the data on the bus.

This type of bus also implements a split transaction model; in classic PCI, a transaction was atomic - that is, once a write, read or configuration cycle started, it had to complete before any other transaction could take place.

In PCI Express (and in PCI-X before it) a transaction could start and not complete immediately, allowing other bus transactions to take place while responses could be delayed. In PCI express (where the data may go across many hops to go from source to destination) this is an absolute must to prevent significant delays.

PCI express uses credit based flow control; this is a form of back pressure control which helps prevent any single node from hogging a link.

PCI Express has many similarities to Infiniband (Intel was a major part of the IBTA when I was part of it) and uses the same concept of lanes (a single differential pair) that can be grouped with other lanes to achieve higher throughput on a given link.

x1, x2, x4 x8, x16 and x32 are all used with the x32 meaning that 32 pairs have been grouped into a single physical link of 32 transmit and 32 receive pairs.

Interesting note: a PCI express design is only required to operate at the x1 (a single transmit and receive pair) and the design width (the number of lanes the design expects to use if it is different to x1). A design that expects a x8 link has to operate at the x8 and x1 widths only.

It would take books (indeed, many have been written) to completely describe PCI express (or any of the other high speed serial protocols for that matter) but the above should get you started with some of the key concepts.

(1) The link operates continuously to remain synchronised and due to the fact that it takes time to establish a link from electrically idle; time we do not want to waste.

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    \$\begingroup\$ This is all good information about PCIe, but note that the question is primarily about DDR. The OP only mentioned PCIe in passing, possibly thinking that it uses DDR techniques. You might consider adding this information to the pcie tag description. \$\endgroup\$
    – Dave Tweed
    Nov 4, 2019 at 19:41
  • \$\begingroup\$ Thank you for the detailed answer \$\endgroup\$
    – user220456
    Nov 5, 2019 at 2:24

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