PCI Express is logically mapped the same way as PCI, but physically it is implemented as a number of point to point links. Due to the logically identical layout, the same base code to implement drivers is largely the same between the two types which is clearly very attractive from a driver perspective.
Each link has an associated Link Training Status and State Machine. (Xilinx Application Note).
The base link protocol (once the link between partners is established) is that there is constant electrical activity on the bus using line coded scrambled data even when there are no packets destined for the receiver (1). Versions 1 and 2 use the venerable 8b / 10b encoding and versions 3 and 4 use 128 bit / 130 bit encoding which reduces the line coding overhead significantly.
A scrambler is used to randomise the data on the bus.
This type of bus also implements a split transaction model; in classic PCI, a transaction was atomic - that is, once a write, read or configuration cycle started, it had to complete before any other transaction could take place.
In PCI Express (and in PCI-X before it) a transaction could start and not complete immediately, allowing other bus transactions to take place while responses could be delayed. In PCI express (where the data may go across many hops to go from source to destination) this is an absolute must to prevent significant delays.
PCI express uses credit based flow control; this is a form of back pressure control which helps prevent any single node from hogging a link.
PCI Express has many similarities to Infiniband (Intel was a major part of the IBTA when I was part of it) and uses the same concept of lanes (a single differential pair) that can be grouped with other lanes to achieve higher throughput on a given link.
x1, x2, x4 x8, x16 and x32 are all used with the x32 meaning that 32 pairs have been grouped into a single physical link of 32 transmit and 32 receive pairs.
Interesting note: a PCI express design is only required to operate at the x1 (a single transmit and receive pair) and the design width (the number of lanes the design expects to use if it is different to x1). A design that expects a x8 link has to operate at the x8 and x1 widths only.
It would take books (indeed, many have been written) to completely describe PCI express (or any of the other high speed serial protocols for that matter) but the above should get you started with some of the key concepts.
(1) The link operates continuously to remain synchronised and due to the fact that it takes time to establish a link from electrically idle; time we do not want to waste.