What is the relationship between input phase and output phase of a pll(phase locked loop)?
Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same phase as input?
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Sign up to join this communityWhat is the relationship between input phase and output phase of a pll(phase locked loop)?
Why is it called phase locked? Does it keeps/locks output phase to phase of input meaning output has same phase as input?
"Phase locked" means that the fundamental feedback mechanism is comparing the phase of the output with the phase of the reference signal, maintaining a constant relationship between them.
The phase offset is not necessarily zero — it depends on the design of the phase detector. Some enforce an offset of 90° or 180°.
Following up on Dave Tweed answer, the PLL will have leakage currents, thus the UP and the Down pulses will be imbalanced to correct for the leakages.
Leakage currents, such as base-currents into NPN bipolar integrators to compare the UP with Down pulses, will cause large Reference Frequency spurs.
When I diagnosed this, I changed to a Darlington integrator.