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I am trying to learn PLL from a website

https://www.allaboutcircuits.com/technical-articles/what-exactly-is-a-phase-locked-loop-anyways/

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I came across a sentence containin[g the term "lock" twice ,1st for frequency and then for phase as shown highlight in attached photo

What is the simple meaning of "lock" in both these scenarios of phase and frequency?

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In a PLL, being "in lock" means that both signals that enter the phase detector are in phase. The phase detector could for example be implemented such that it will ouput:

  • a negative output voltage \$V_1\$ when the rising edge of \$\phi_2\$ occurs first (before the rising edge of \$\phi_2\$)
  • a zero output voltage \$V_1\$ when the rising edges of the input signals occur at the same moment
  • a positive output voltage \$V_1\$ when the rising edge of \$\phi_1\$ occurs first (before the rising edge of \$\phi_2\$)

enter image description here

With such a phase detector, the loop will strive to make the phase difference (between \$\phi_1\$ and \$\phi_2\$) zero. When that is achieved, the PLL is locked.

Then the rising edges of \$\phi_1\$ and \$\phi_2\$ occur at the same time. That then also means that their frequency is the same.

If that was not the case (the frequencies are different) and for example \$\phi_1\$ has a higher frequency than \$\phi_2\$, the rising edge of \$\phi_1\$ would occur before the rising edge of \$\phi_2\$ and then the PLL would not be locked! Then \$V_1\$ would become positive (\$\phi_1\$'s edge occurs first) which would increase \$V_2\$ and with that increase the frequency of \$\phi_2\$. That would continue until the PLL locks again (assuming the locking frequency can be achieved by the VCO).

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