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I've came across some products that help you troubleshoot a computer that won't POST, with listening and capturing traffic on PCI bus during system startup.

They essentially know the normal procedure, and can tell you what is not going on as expected.

I know conventional PCI is a shared Bus, which means you can sniff the traffic that is not even addressed to you just by listening on the bus. You don't even have to introduce yourself to the controller since you are not going to send anything.

But these cards have a PCIe port too. Isn't PCIe a Peer-to-Peer connection? How are they capturing traffic that is targeted to other devices?

And is it possible to use an FPGA that doesn't have a dedicated PCIe endpoint integrated and isn't fast enough to operate on a 2GHz bus? Does the bus operate on a lower speed during POST or device initialization?

And after all, is it gonna work on newer hardware? Do they broadcast any useful messages during POST?

Thanks.

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  • \$\begingroup\$ I used to use an FPGA board tied into the PCI bus to test for chipset bugs. But that was PCI, not PCIe, since at the time PCIe didn't exist. Also, I was working with PCI bus rates of 33 MHz (2 ns clock skew) and 66 MHz (1 ns clock skew) at the time. Then, unbridged PCI supported 10 loads (which given two bridge chips meant 4 devices as a connector used up a load and so did a board, making 2 loads per board.) At the time, the front-side bus was clocked at high speed nearer the CPU rates (back-side bus existed only inside the CPU package between L2 cache and CPU+L1.) Are you saying PCI is 2 GHz? \$\endgroup\$
    – jonk
    Nov 5 '19 at 21:38
  • \$\begingroup\$ Those boards don't snoop traffic, they look for the bios/bootloader/efi or whatever to send them diagnostic information. \$\endgroup\$ Nov 5 '19 at 22:09
  • \$\begingroup\$ @jonk: No, he's saying PCIe 1.0 is 2 Gbps (2.5 GTPS) maximum per lane. \$\endgroup\$
    – Dave Tweed
    Nov 5 '19 at 22:12
  • \$\begingroup\$ @Dave Thanks. My limited experience didn't let me see that readily. I misapplied parts from another paragraph. Appreciated. \$\endgroup\$
    – jonk
    Nov 5 '19 at 22:13
  • \$\begingroup\$ PCIe does not, by itself, define any form of POST; it does look for link partners and attempt to establish a link if a link partner is detected. The sense is a pulse transmitted (every 6 mSec I believe) when in the polling state in the LTSSM and the reflection is measured. If a partner is sensed, the link immediately goes to 2.5Gb/sec (it may go higher during link up but it always starts at the rev 1 rate). \$\endgroup\$ Nov 6 '19 at 9:41
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PCIe is peer to peer so it's not possible to snoop on traffic to another card, unless you physically connect something to a PCIe link that the data traverses. I'm not sure what those POST cards are doing, but presumably it's not sniffing.

It is possible to use an FPGA that doesn't have a hard PCIe endpoint, it just requires building a PCIe endpoint in soft logic. The main thing the FPGA needs are the high speed serializers that support operation at the PCIe link rate - at least 2.5 Gbps so you can bring up a PCIe gen 1 link.

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