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I am trying to understand common mode voltage a little bit fundamentally (only with electronic devices and no math).

I watched this Youtube Video to understand common mode and differential mode voltage.

When he explains the circuit and draws the waveform, the waveforms represent the voltage at the collector or the voltage at the base? (let us assume they are transistors for simplicity instead of MOSFETs) Are those sine waves taken at the base of the transistors or at their collectors?

Please tell me whether my understanding is correct :

So, in this type of circuit, we always need to bias the transistors when we need to use them as amplifiers. So, while biasing, we set the voltage at the collector with the help of the collector resistor, right? So, the voltage measured at the collector of the transistor during OFF condition of the transistor is called as the common mode voltage right?

This is Another video which I referred to understand the biasing of transistors when they need to be used as amplifiers

And this voltage is the bias voltage of the transistors which is 1.2V (Common mode voltage of LVDS) incase of LVDS driver circuit right?

Can someone tell me whether I am right or wrong? If I am wrong, please explain me the concept of common mode voltage with out math and only with the transistors and electronics. Please.

I have previously asked the question regarding the LVDS Common Mode Voltage here I haven't accepted the answers because I was not able to get clarity. Can someone please break this concept in very simple terms?

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  • \$\begingroup\$ Please use the right terms and please don't ask to have youtube videos explained because, as you have found, it's unclear whether they talk about gate voltage or drain voltage. Also, in this type of amplifier the transistors (yes MOSFETs are also transistors) are never fully on or fully off. \$\endgroup\$ – Andy aka Nov 7 '19 at 11:24
  • \$\begingroup\$ I am trying to let you all know where I get all the information that I have researched. And sure. I would not post video here in future. But could you answer my question regarding the common mode voltage understanding with transistors and whether my understanding regarding LVDS is correct? \$\endgroup\$ – Newbie Nov 7 '19 at 11:29
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LVDS signalling is depicted here on the right: -

enter image description here

Link to website where I stole the picture.

The common mode voltage is the average voltage of the upper and lower digital values. Upper is 1.40 volts and lower is 1.05 volts hence, the common mode voltage is 1.225 volts.

So, as you can see the transistors are neither fully on nor fully off but biased at 1.225 volts. Reason: you won't get high speed data with fully turned on or off transistors (as in CMOS).

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  • \$\begingroup\$ Thank you. So, the voltage of 1.225V is measured at the collector of the transistor, right? And when you mean not fully on and not fully off, you mean they are working in the active region right? Please clear both my doubts \$\endgroup\$ – Newbie Nov 7 '19 at 11:39
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    \$\begingroup\$ I prefer to use the term linear region. However, I cannot say (for just one transistor) whether the base/gate is at 1.225 volts because the LVDS is an input/output specification and, the actual chips that implement it are generally unclear whether the input connects directly to the base/gate of a transistor or via something else. Ditto the collector/drain. \$\endgroup\$ – Andy aka Nov 7 '19 at 11:50
  • \$\begingroup\$ Thank you for the answer. One last question. So, transistors used in these types of circuits work in the linear region , right ? \$\endgroup\$ – Newbie Nov 7 '19 at 12:14
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    \$\begingroup\$ That's correct; not saturated and not off. Trying to "get out" from saturation or off condition takes a lot of time (relatively speaking) and that will piss on data speeds. \$\endgroup\$ – Andy aka Nov 7 '19 at 12:15
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    \$\begingroup\$ Repeating what I said earlier in a comment: I cannot say (for just one transistor) whether the base/gate is at 1.225 volts because the LVDS is an input/output specification and, the actual chips that implement it are generally unclear whether the input connects directly to the base/gate of a transistor or via something else. \$\endgroup\$ – Andy aka Nov 7 '19 at 12:56

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