# Bias voltage of transistor [closed]

I would like to understand the purpose of biasing the transistor and why It has to be halfway between Vcc and ground?

And which terminal of the transistor (Base, collector or emitter) should be between halfway between Vcc and ground while biasing.

An analogy would help a lot. Please

• why It has to be halfway between Vcc and ground? Who says it has to? You can also bias a circuit in a different way. It depends on what you want to achieve with the circuit. Have you read: allaboutcircuits.com/textbook/semiconductors/chpt-4/… ? – Bimpelrekkie Nov 7 '19 at 13:05
• I read it somewhere that when it is biased between Vcc and ground at halfway, we can get the maximum swing at the output voltage. Could you please clarify. – Newbie Nov 7 '19 at 13:06
• we can get the maximum swing at the output voltage Aha! Now what terminal of the transistor connects to the output? – Bimpelrekkie Nov 7 '19 at 13:07
• I think this question has already been asked and answered here – Peter Jennings Nov 7 '19 at 13:16
• why do we bias transistors to operate the transistor in a sort of "linear" fashion so that it can amplify signals. There is plenty of information to be found about that in books and the internet, there really is no need to explain that in detail here. – Bimpelrekkie Nov 7 '19 at 13:17

It is the collector DC voltage that ought to be midway biased to the positive supply to allow for larger symmetrical output swing.

## Other details

A far better design is to incorporate negative feedback, which is a bit more complicated due to load/source impedance ratios, but works much better for large signal , very low THD, high gain, lower tolerance sensitivity but lower input impedance. These are all tradeoffs in a discrete design.

You know that current gain, hFE in a transistor is not constant and into a collector resistor that represents voltage gain.

You can review a range of discrete data sheets from table values worst case or curves to show the trends.

Generally hFE reduces 50% when due to AC input, the collector current drops to 1% without negative feedback. Also when Vce reduces from < 1V to Vce(sat), the hFE reduces rapidly towards 10% of hFE typ.

Thus ideally the DC collector idle voltage should be near Vcc/2 and current variation <+/-10%. This implies +/-10% of full swing. But if THD is not so important then a bigger swing is possible.

Here you see large swing tradeoffs of high gain and very nonlinear (top) or very low voltage gain (bottom). But attempts to center Vc = Vcc/2 for symmetrical full swing if needed.