It is the collector DC voltage that ought to be midway biased to the positive supply to allow for larger symmetrical output swing.
A far better design is to incorporate negative feedback, which is a bit more complicated due to load/source impedance ratios, but works much better for large signal , very low THD, high gain, lower tolerance sensitivity but lower input impedance. These are all tradeoffs in a discrete design.
You know that current gain, hFE in a transistor is not constant and into a collector resistor that represents voltage gain.
You can review a range of discrete data sheets from table values worst case or curves to show the trends.
Generally hFE reduces 50% when due to AC input, the collector current drops to 1% without negative feedback. Also when Vce reduces from < 1V to Vce(sat), the hFE reduces rapidly towards 10% of hFE typ.
Thus ideally the DC collector idle voltage should be near Vcc/2 and current variation <+/-10%. This implies +/-10% of full swing. But if THD is not so important then a bigger swing is possible.
Here you see large swing tradeoffs of high gain and very nonlinear (top) or very low voltage gain (bottom). But attempts to center Vc = Vcc/2 for symmetrical full swing if needed.