I'm interested in trying to estimate the worst-case error when using a particular DFT implementation (CMSIS) and an ADC and voltage reference with known error bounds.
I think that I can work out the math itself without much issue, but I'm not clear what "worst-case" looks like.
I have a vibrating string with constant fundamental harmonic frequency (like a guitar string) per "pluck" - the frequency can change from pluck to pluck though. The fundamental frequency should have the highest magnitude by a good margin, so higher-order harmonics and outside noise should not present too much problem.
So if I assume that my ADC is, say, +-2 LSB at 2kSamples/s (using a sample size of 1024 points with a perfect voltage reference), and I look at a simple sine wave of representative frequency, what would the worst case look like?
- Would it be if the ADC alternated between +2 and -2 LSB on each measurement?
- Or maybe it would "throw off" FFT more to have every measurement be +2 LSB for a certain time then all of a sudden be -2 LSB?
Clearly (?) there is some point where you want to ADC measurements to be off by its extremes, otherwise its just a translation of the wave.
- Has anyone seen a resource for figuring out this kind of thing before? Or is it better just to run a few thousand examples and do a statistical analysis to determine likely bounds?
My motivation is to discover if I can know a priori if I should go with an ADC of less precision and accuracy, i.e. if a certain ADC is overkill.