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I've been reading about external peripheral mapping to microcontrollers.

I understand that memory-mapped IO means that the same address space in the microcontroller can be used for internal memory and also to map external peripherals. Therefore the same instructions we normally use can be used to communicate with external devices.

Port-mapped IO means that there is a certain address space especially used for mapping external peripherals. Sometimes specific instructions need to be used to accesss the peripherals via this address space.

Obviously we can see the advantages of memory-mapped IO here. However, I read from the link below that

"The disadvantage of memory-mapped IO method is that the entire address bus must be fully decoded for every device. For example, a machine with a 32-bit address bus would require logic gates to resolve the state of all 32 address lines to properly decode the specific address of any device. This increases the cost of adding hardware to the machine."

Can someone please explain this as I can't understand this. Why does the microcontroller need to decode the 32-bit address bus like this?

https://www.bogotobogo.com/Embedded/memory_mapped_io_vs_port_mapped_isolated_io.php

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  • \$\begingroup\$ are you familiar with what is address decoding \$\endgroup\$ – Mitu Raj Nov 8 '19 at 9:25
  • \$\begingroup\$ Well, you don't have to decode the entire bus but then you end up with unavailable address space (a particular peripheral can have more than one address). \$\endgroup\$ – Peter Smith Nov 8 '19 at 9:30
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The statement as it stand is false or least incomplete.

Normally an I/O instruction activates some special pins on the controller to distinguish the I/O operation from a memory operation.

The statement above seems to assume that the I/O instruction then uses only part of the 32-bit address bus and thus less address decoding is needed. Without mentioning this the statement is, by itself false.

Note that, especially in the early days of the micro-controllers, whole sections of the address map would be mapped onto a few peripherals by using a few address lines to select all peripherals. e.g. address lines 15 and 14 would select one of three peripherals leaving 16K as address space.

This technique is still widely used.
These days a 32-bit processor has 2G address space but many micro-controllers have less then 1M of memory (in Flash and RAM) requiring only 20 address lines. This leaves many spare address lines for this type of sparse decoding.

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  • \$\begingroup\$ I don't think your statements about "sparse decoding" are applicable any more. For example, the Cortex-M processors I work with have thousands of I/O device registers and accessing them requires that, somehow, all 32 bits of the address are decoded. \$\endgroup\$ – Elliot Alderson Nov 8 '19 at 12:52
  • \$\begingroup\$ @ElliotAlderson Those are on-chip devices and thus on-chip decoding. I was talking about the off-chip decoding practices. The on-chip decoding logic for 32 bits is only a tiny fraction of the gates needed to implement e.g. the AXI protocol. Having built SOCs with ARM AXI buses my guesstimate is that the decoding logic is less then 0.1% of the AXI bus which is often less then 1% of the chip gates. \$\endgroup\$ – Oldfart Nov 8 '19 at 16:34
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Why does the microcontroller need to decode the 32-bit address bus like this?

With memory mapped I/O the address must be decoded sufficiently to separate the I/O and memory areas. The fewer address lines that are used to select each block, the larger the block will be and the more space could be wasted. In a 32 bit MCU you could just decode A31 to eg. put memory in the first 2GB and I/O in the second 2GB. With 2GB of memory space still available that probably isn't a problem, but in an MCU with 16 or fewer address bits it would severely reduce the available memory space.

With separate I/O space the I/O instructions cause a different enable line to be activated, so memory devices don't respond even if they are on the same address. Now the I/O devices can use a subset of the address lines and ignore the others, and the I/O instructions don't need to specify a full width address.

Historically, most early MCUs were designed around an existing CPU with embedded peripherals, with a small (or no) internal ROM and the ability to use external memory. Those based on the Intel 8080 etc. had separate I/O space, while those based on the Motorola 6800 had memory mapped I/O. These early MCUs had few transistors and small memory space, so the savings from having separate I/O space could be significant. It meant that maximum memory space was available with no 'holes', and I/O devices needed less decoding logic.

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